[PATCH] D61491: AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL363516: AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0 (authored by nha, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D61491?vs=197959&id=204960#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61491/new/

https://reviews.llvm.org/D61491

Files:
  llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
  llvm/trunk/test/CodeGen/AMDGPU/llvm.memcpy.ll
  llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll


Index: llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=GCN
 ; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -r --symbols | FileCheck %s -check-prefix=EG
 
-; GCN: R_AMDGPU_REL32 extern_const_addrspace
+; GCN: R_AMDGPU_REL32_LO extern_const_addrspace
 ; EG: R_AMDGPU_ABS32 extern_const_addrspace
 
 ; CHECK-DAG: Name: extern_const_addrspace
Index: llvm/trunk/test/CodeGen/AMDGPU/llvm.memcpy.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.memcpy.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.memcpy.ll
@@ -333,7 +333,7 @@
 
 ; FUNC-LABEL: {{^}}test_memcpy_const_string_align4:
 ; SI: s_getpc_b64
-; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4+20
+; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4 at rel32@lo+20
 ; SI: s_addc_u32
 ; SI-DAG: s_load_dwordx4
 ; SI-DAG: s_load_dwordx4
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1369,10 +1369,7 @@
 
     MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
                                   .addReg(RegHi);
-    if (MI.getOperand(2).getTargetFlags() == SIInstrInfo::MO_NONE)
-      MIB.addImm(0);
-    else
-      MIB.add(MI.getOperand(2));
+    MIB.add(MI.getOperand(2));
 
     Bundler.append(MIB);
     finalizeBundle(MBB, Bundler.begin());
Index: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -4644,11 +4644,18 @@
   // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
   // small. This requires us to add 4 to the global variable offset in order to
   // compute the correct address.
-  SDValue PtrLo = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
-                                             GAFlags);
-  SDValue PtrHi = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
-                                             GAFlags == SIInstrInfo::MO_NONE ?
-                                             GAFlags : GAFlags + 1);
+  unsigned LoFlags = GAFlags;
+  if (LoFlags == SIInstrInfo::MO_NONE)
+    LoFlags = SIInstrInfo::MO_REL32;
+  SDValue PtrLo =
+      DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, LoFlags);
+  SDValue PtrHi;
+  if (GAFlags == SIInstrInfo::MO_NONE) {
+    PtrHi = DAG.getTargetConstant(0, DL, MVT::i32);
+  } else {
+    PtrHi =
+        DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4, GAFlags + 1);
+  }
   return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
 }
 
Index: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
@@ -551,11 +551,16 @@
   (outs SReg_64:$dst),
   (ins si_ga:$ptr_lo, si_ga:$ptr_hi),
   [(set SReg_64:$dst,
-   (i64 (SIpc_add_rel_offset (tglobaladdr:$ptr_lo), (tglobaladdr:$ptr_hi))))]> {
+      (i64 (SIpc_add_rel_offset tglobaladdr:$ptr_lo, tglobaladdr:$ptr_hi)))]> {
   let Defs = [SCC];
 }
 
 def : GCNPat <
+  (SIpc_add_rel_offset tglobaladdr:$ptr_lo, 0),
+  (SI_PC_ADD_REL_OFFSET $ptr_lo, (i32 0))
+>;
+
+def : GCNPat <
   (AMDGPUinit_exec i64:$src),
   (SI_INIT_EXEC (as_i64imm $src))
 >;


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