[PATCH] D63351: [AMDGPU] gfx10 conditional registers handling

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: kzhuravl, msearles, arsenm.
Herald added subscribers: jsji, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely.

This is cpp source part of wave32 support, excluding overriden
getRegClass().

This is another split from D63204 <https://reviews.llvm.org/D63204> to reduce it.


https://reviews.llvm.org/D63351

Files:
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInsertSkips.cpp
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  lib/Target/AMDGPU/SILowerI1Copies.cpp
  lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  lib/Target/AMDGPU/SIWholeQuadMode.cpp
  test/CodeGen/AMDGPU/mubuf-legalize-operands.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63351.204824.patch
Type: text/x-patch
Size: 99153 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190614/b420cd0d/attachment-0001.bin>