[llvm] r363501 - [X86] CombineShuffleWithExtract - assert all src ops types are multiples of rootsize. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sat Jun 15 12:12:44 2019
New Revision: 363501

URL: http://llvm.org/viewvc/llvm-project?rev=363501&view=rev
Log:
[X86] CombineShuffleWithExtract - assert all src ops types are multiples of rootsize. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=363501&r1=363500&r2=363501&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jun 15 12:12:44 2019
@@ -31960,7 +31960,8 @@ static SDValue combineX86ShuffleChain(Ar
     unsigned Offset2 = V2.getConstantOperandVal(1);
     assert(((Offset1 % VT1.getVectorNumElements()) == 0 ||
             (Offset2 % VT2.getVectorNumElements()) == 0 ||
-            (Src1.getValueSizeInBits() % RootSizeInBits) == 0) &&
+            (Src1.getValueSizeInBits() % RootSizeInBits) == 0 ||
+            (Src2.getValueSizeInBits() % RootSizeInBits) == 0) &&
            "Unexpected subvector extraction");
     unsigned Scale = Src1.getValueSizeInBits() / RootSizeInBits;