[llvm] r363476 - Revert "GlobalISel: Avoid producing Illegal copies in RegBankSelect"
Mitch Phillips via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 14 16:45:35 PDT 2019
Author: hctim
Date: Fri Jun 14 16:45:34 2019
New Revision: 363476
URL: http://llvm.org/viewvc/llvm-project?rev=363476&view=rev
Log:
Revert "GlobalISel: Avoid producing Illegal copies in RegBankSelect"
This patch breaks UBSan build bots. See
https://github.com/google/sanitizers/wiki/SanitizerBotReproduceBuild for
a guide as to how to reproduce the error.
This reverts commit c2864c0de07efb5451d32d27a7d4ff2984830929.
This reverts rL363410.
Removed:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h?rev=363476&r1=363475&r2=363476&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h Fri Jun 14 16:45:34 2019
@@ -617,12 +617,6 @@ public:
return &A != &B;
}
- /// \returns true if emitting a copy from \p Src to \p Dst is impossible.
- bool cannotCopy(const RegisterBank &Dst, const RegisterBank &Src,
- unsigned Size) const {
- return copyCost(Dst, Src, Size) == std::numeric_limits<unsigned>::max();
- }
-
/// Get the cost of using \p ValMapping to decompose a register. This is
/// similar to ::copyCost, except for cases where multiple copy-like
/// operations need to be inserted. If the register is used as a source
Modified: llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp?rev=363476&r1=363475&r2=363476&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp Fri Jun 14 16:45:34 2019
@@ -220,35 +220,18 @@ RegisterBankInfo::getInstrMappingImpl(co
} else {
OperandsMapping[0] = ValMapping;
}
- }
- // The default handling assumes any register bank can be copied to any
- // other. If this isn't the case, the target should specially deal with
- // reg_sequence/phi. There may also be unsatisfiable copies.
- for (; OpIdx != EndIdx; ++OpIdx) {
- const MachineOperand &MO = MI.getOperand(OpIdx);
- if (!MO.isReg())
- continue;
- unsigned Reg = MO.getReg();
- if (!Reg)
- continue;
-
- const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI);
- if (cannotCopy(*CurRegBank, *AltRegBank, getSizeInBits(Reg, MRI, TRI)))
- return getInvalidInstructionMapping();
+ CompleteMapping = true;
}
- CompleteMapping = true;
break;
}
-
OperandsMapping[OpIdx] = ValMapping;
}
- if (IsCopyLike && !CompleteMapping) {
+ if (IsCopyLike && !CompleteMapping)
// No way to deduce the type from what we have.
return getInvalidInstructionMapping();
- }
assert(CompleteMapping && "Setting an uncomplete mapping");
return getInstructionMapping(
@@ -407,12 +390,8 @@ RegisterBankInfo::getInstrMapping(const
RegisterBankInfo::InstructionMappings
RegisterBankInfo::getInstrPossibleMappings(const MachineInstr &MI) const {
InstructionMappings PossibleMappings;
- const auto &Mapping = getInstrMapping(MI);
- if (Mapping.isValid()) {
- // Put the default mapping first.
- PossibleMappings.push_back(&Mapping);
- }
-
+ // Put the default mapping first.
+ PossibleMappings.push_back(&getInstrMapping(MI));
// Then the alternative mapping, if any.
InstructionMappings AltMappings = getInstrAlternativeMappings(MI);
for (const InstructionMapping *AltMapping : AltMappings)
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp?rev=363476&r1=363475&r2=363476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp Fri Jun 14 16:45:34 2019
@@ -991,81 +991,13 @@ AMDGPURegisterBankInfo::getRegBankID(uns
///
const RegisterBankInfo::InstructionMapping &
AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
- const MachineFunction &MF = *MI.getParent()->getParent();
- const MachineRegisterInfo &MRI = MF.getRegInfo();
-
- if (MI.isRegSequence()) {
- // If any input is a VGPR, the result must be a VGPR. The default handling
- // assumes any copy between banks is legal.
- unsigned BankID = AMDGPU::SGPRRegBankID;
-
- for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
- auto OpBank = getRegBankID(MI.getOperand(I).getReg(), MRI, *TRI);
- // It doesn't make sense to use vcc or scc banks here, so just ignore
- // them.
- if (OpBank != AMDGPU::SGPRRegBankID) {
- BankID = AMDGPU::VGPRRegBankID;
- break;
- }
- }
- unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
-
- const ValueMapping &ValMap = getValueMapping(0, Size, getRegBank(BankID));
- return getInstructionMapping(
- 1, /*Cost*/ 1,
- /*OperandsMapping*/ getOperandsMapping({&ValMap}), 1);
- }
-
- // The default handling is broken and doesn't handle illegal SGPR->VGPR copies
- // properly.
- //
- // TODO: There are additional exec masking dependencies to analyze.
- if (MI.getOpcode() == TargetOpcode::G_PHI) {
- // TODO: Generate proper invalid bank enum.
- int ResultBank = -1;
-
- for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
- unsigned Reg = MI.getOperand(I).getReg();
- const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI);
-
- // FIXME: Assuming VGPR for any undetermined inputs.
- if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) {
- ResultBank = AMDGPU::VGPRRegBankID;
- break;
- }
-
- unsigned OpBank = Bank->getID();
- // scc, scc -> sgpr
- if (OpBank == AMDGPU::SCCRegBankID) {
- // There's only one SCC register, so a phi requires copying to SGPR.
- OpBank = AMDGPU::SGPRRegBankID;
- } else if (OpBank == AMDGPU::VCCRegBankID) {
- // vcc, vcc -> vcc
- // vcc, sgpr -> vgpr
- if (ResultBank != -1 && ResultBank != AMDGPU::VCCRegBankID) {
- ResultBank = AMDGPU::VGPRRegBankID;
- break;
- }
- }
-
- ResultBank = OpBank;
- }
-
- assert(ResultBank != -1);
-
- unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
-
- const ValueMapping &ValMap =
- getValueMapping(0, Size, getRegBank(ResultBank));
- return getInstructionMapping(
- 1, /*Cost*/ 1,
- /*OperandsMapping*/ getOperandsMapping({&ValMap}), 1);
- }
-
const RegisterBankInfo::InstructionMapping &Mapping = getInstrMappingImpl(MI);
+
if (Mapping.isValid())
return Mapping;
+ const MachineFunction &MF = *MI.getParent()->getParent();
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<const ValueMapping*, 8> OpdsMapping(MI.getNumOperands());
switch (MI.getOpcode()) {
Removed: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir?rev=363475&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir (removed)
@@ -1,18 +0,0 @@
-# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-fast %s -o /dev/null 2>&1 | FileCheck %s
-# RUN: not llc -march=amdgcn -run-pass=regbankselect -regbankselect-greedy %s -o /dev/null 2>&1 | FileCheck %s
-
-# Check behavior for illegal copies.
-
-# CHECK: LLVM ERROR: unable to map instruction: $sgpr0 = COPY %0:vgpr(s32) (in function: illegal_copy_s32_v_to_s)
-
----
-name: illegal_copy_s32_v_to_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0
-
- %0:_(s32) = COPY $vgpr0
- $sgpr0 = COPY %0
-...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir?rev=363476&r1=363475&r2=363476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir Fri Jun 14 16:45:34 2019
@@ -74,7 +74,7 @@ body: |
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
@@ -273,7 +273,7 @@ body: |
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
@@ -424,11 +424,8 @@ body: |
; CHECK: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; CHECK: [[PHI:%[0-9]+]]:scc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[PHI]](s1), [[C]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -489,11 +486,8 @@ body: |
; CHECK: [[ICMP4:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C3]]
; CHECK: G_BR %bb.3
; CHECK: bb.3:
- ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1, [[ICMP4]](s1), %bb.2
- ; CHECK: [[COPY4:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY4]](s1), [[COPY5]], [[COPY6]]
+ ; CHECK: [[PHI:%[0-9]+]]:scc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1, [[ICMP4]](s1), %bb.2
+ ; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[PHI]](s1), [[COPY]], [[COPY1]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.3
@@ -556,11 +550,8 @@ body: |
; CHECK: [[ICMP2:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; CHECK: [[PHI:%[0-9]+]]:scc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[PHI]](s1), [[C]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -611,11 +602,10 @@ body: |
; CHECK: [[ICMP2:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; CHECK: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY4]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -774,11 +764,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; CHECK: [[PHI:%[0-9]+]]:scc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[PHI]](s1), [[C]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -829,11 +816,8 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY5]]
+ ; CHECK: [[PHI:%[0-9]+]]:scc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; CHECK: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[PHI]](s1), [[C]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -938,10 +922,9 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
+ ; CHECK: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -992,7 +975,7 @@ body: |
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[ICMP1]](s1), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[ICMP1]](s1), %bb.1
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
@@ -1047,10 +1030,9 @@ body: |
; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
- ; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
- ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
- ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY3]](s1), [[COPY4]], [[COPY]]
+ ; CHECK: [[PHI:%[0-9]+]]:vcc(s1) = G_PHI [[ICMP]](s1), %bb.0, [[TRUNC]](s1), %bb.1
+ ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+ ; CHECK: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[PHI]](s1), [[COPY3]], [[COPY]]
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31, implicit [[SELECT]](s32)
bb.0:
successors: %bb.1, %bb.2
@@ -1209,7 +1191,7 @@ body: |
; CHECK: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: G_BR %bb.2
; CHECK: bb.2:
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[TRUNC1]](s1), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[TRUNC]](s1), %bb.0, [[TRUNC1]](s1), %bb.1
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[PHI]](s1)
; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
@@ -1368,7 +1350,7 @@ body: |
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %5(s32), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %5(s32), %bb.1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
@@ -1417,7 +1399,7 @@ body: |
; CHECK: G_BR %bb.1
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %5(s32), %bb.1
+ ; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %5(s32), %bb.1
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[COPY2]](s32)
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
@@ -1447,99 +1429,3 @@ body: |
S_SETPC_B64 undef $sgpr30_sgpr31, implicit %4
...
-
----
-name: phi_s32_ss_sbranch_cycle
-legalized: true
-tracksRegLiveness: true
-
-body: |
- ; CHECK-LABEL: name: phi_s32_ss_sbranch_cycle
- ; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
- ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %6(s32), %bb.2
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[PHI]](s32), %bb.1
- ; CHECK: G_BR %bb.1
- bb.0:
- successors: %bb.1, %bb.2
- liveins: $sgpr0, $sgpr1, $sgpr2
-
- %0:_(s32) = COPY $sgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s32) = COPY $sgpr2
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(s1) = G_ICMP intpred(eq), %2, %3
- G_BRCOND %4, %bb.1
- G_BR %bb.2
-
- bb.1:
- successors: %bb.2
- %5:_(s32) = G_PHI %0, %bb.0, %6, %bb.2
- G_BR %bb.2
-
- bb.2:
- successors: %bb.1
- %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- G_BR %bb.1
-...
-
----
-name: phi_s32_vs_sbranch_cycle
-legalized: true
-tracksRegLiveness: true
-
-body: |
- ; CHECK-LABEL: name: phi_s32_vs_sbranch_cycle
- ; CHECK: bb.0:
- ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
- ; CHECK: liveins: $vgpr0, $sgpr1, $sgpr2
- ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2
- ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
- ; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
- ; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.1:
- ; CHECK: successors: %bb.2(0x80000000)
- ; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, %6(s32), %bb.2
- ; CHECK: G_BR %bb.2
- ; CHECK: bb.2:
- ; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: [[PHI1:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[PHI]](s32), %bb.1
- ; CHECK: G_BR %bb.1
- bb.0:
- successors: %bb.1, %bb.2
- liveins: $vgpr0, $sgpr1, $sgpr2
-
- %0:_(s32) = COPY $vgpr0
- %1:_(s32) = COPY $sgpr1
- %2:_(s32) = COPY $sgpr2
- %3:_(s32) = G_CONSTANT i32 0
- %4:_(s1) = G_ICMP intpred(eq), %2, %3
- G_BRCOND %4, %bb.1
- G_BR %bb.2
-
- bb.1:
- successors: %bb.2
- %5:_(s32) = G_PHI %0, %bb.0, %6, %bb.2
- G_BR %bb.2
-
- bb.2:
- successors: %bb.1
- %6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- G_BR %bb.1
-...
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir?rev=363476&r1=363475&r2=363476&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir Fri Jun 14 16:45:34 2019
@@ -49,7 +49,7 @@ body: |
; CHECK: liveins: $sgpr0, $vgpr0
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE [[COPY]](s32), %subreg.sub0, [[COPY1]](s32), %subreg.sub1
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
@@ -66,7 +66,7 @@ body: |
; CHECK-LABEL: name: reg_sequence_sv_physreg
; CHECK: liveins: $sgpr0, $vgpr0
- ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
+ ; CHECK: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
%0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
...
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