[PATCH] D63364: [x86] split 256-bit vector selects if operands are vector concats

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, lebedev.ri.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

This is similar logic/motivation to the select splitting in D62969 <https://reviews.llvm.org/D62969>.

In D63233 <https://reviews.llvm.org/D63233>, the pattern changes so that we no longer have an extract_subvector of vselect, but the operands of the select are still being concatenated.

The closest case is represented in either the first or last test diffs here - we have an extra instruction, but we converted 3-4 ymm instructions into 4-5 xmm instructions. I think that's the right trade-off for most AVX1 targets.

In the example based on PR37428:
https://bugs.llvm.org/show_bug.cgi?id=37428
...this makes the loop about 30% faster (tested on Haswell by compiling with -mavx).


https://reviews.llvm.org/D63364

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/cast-vsel.ll
  llvm/test/CodeGen/X86/known-signbits-vector.ll
  llvm/test/CodeGen/X86/vselect-avx.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D63364.204857.patch
Type: text/x-patch
Size: 11015 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190614/9ff03fb7/attachment.bin>