[llvm] r363403 - [ARM] Add MVE horizontal accumulation instructions
Mikhail Maltsev via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 14 07:31:14 PDT 2019
Author: miyuki
Date: Fri Jun 14 07:31:13 2019
New Revision: 363403
URL: http://llvm.org/viewvc/llvm-project?rev=363403&view=rev
Log:
[ARM] Add MVE horizontal accumulation instructions
This is the family of vector instructions that combine all the lanes
in their input vector(s), and output a value in one or two GPRs.
Differential Revision: https://reviews.llvm.org/D62670
Added:
llvm/trunk/test/MC/ARM/mve-reductions-fp.s
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
llvm/trunk/test/MC/ARM/mve-reductions.s
llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=363403&r1=363402&r2=363403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Fri Jun 14 07:31:13 2019
@@ -366,6 +366,8 @@ class VFP3InstAlias<string Asm, dag Resu
: InstAlias<Asm, Result, EmitPriority>, Requires<[HasVFP3]>;
class NEONInstAlias<string Asm, dag Result, bit EmitPriority = 0>
: InstAlias<Asm, Result, EmitPriority>, Requires<[HasNEON]>;
+class MVEInstAlias<string Asm, dag Result, bit EmitPriority = 1>
+ : InstAlias<Asm, Result, EmitPriority>, Requires<[HasMVEInt, IsThumb]>;
class VFP2MnemonicAlias<string src, string dst> : MnemonicAlias<src, dst>,
Modified: llvm/trunk/lib/Target/ARM/ARMInstrMVE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrMVE.td?rev=363403&r1=363402&r2=363403&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrMVE.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrMVE.td Fri Jun 14 07:31:13 2019
@@ -266,6 +266,322 @@ def VABAVu8 : t2VABAV<"u8", 0b1, 0b00>;
def VABAVu16 : t2VABAV<"u16", 0b1, 0b01>;
def VABAVu32 : t2VABAV<"u32", 0b1, 0b10>;
+class t2VADDV<string iname, string suffix, dag iops, string cstr,
+ bit A, bit U, bits<2> size, list<dag> pattern=[]>
+ : MVE_rDest<(outs tGPREven:$Rda), iops, NoItinerary,
+ iname, suffix, "$Rda, $Qm", cstr, pattern> {
+ bits<3> Qm;
+ bits<4> Rda;
+
+ let Inst{28} = U;
+ let Inst{22-20} = 0b111;
+ let Inst{19-18} = size{1-0};
+ let Inst{17-16} = 0b01;
+ let Inst{15-13} = Rda{3-1};
+ let Inst{12} = 0b0;
+ let Inst{8-6} = 0b100;
+ let Inst{5} = A;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = 0b0;
+}
+
+multiclass t2VADDV_A<string suffix, bit U, bits<2> size, list<dag> pattern=[]> {
+ def acc : t2VADDV<"vaddva", suffix,
+ (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
+ 0b1, U, size, pattern>;
+ def no_acc : t2VADDV<"vaddv", suffix,
+ (ins MQPR:$Qm), "",
+ 0b0, U, size, pattern>;
+}
+
+defm VADDVs8 : t2VADDV_A<"s8", 0b0, 0b00>;
+defm VADDVs16 : t2VADDV_A<"s16", 0b0, 0b01>;
+defm VADDVs32 : t2VADDV_A<"s32", 0b0, 0b10>;
+defm VADDVu8 : t2VADDV_A<"u8", 0b1, 0b00>;
+defm VADDVu16 : t2VADDV_A<"u16", 0b1, 0b01>;
+defm VADDVu32 : t2VADDV_A<"u32", 0b1, 0b10>;
+
+class t2VADDLV<string iname, string suffix, dag iops, string cstr,
+ bit A, bit U, list<dag> pattern=[]>
+ : MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, NoItinerary, iname,
+ suffix, "$RdaLo, $RdaHi, $Qm", cstr, pattern> {
+ bits<3> Qm;
+ bits<4> RdaLo;
+ bits<4> RdaHi;
+
+ let Inst{28} = U;
+ let Inst{22-20} = RdaHi{3-1};
+ let Inst{19-18} = 0b10;
+ let Inst{17-16} = 0b01;
+ let Inst{15-13} = RdaLo{3-1};
+ let Inst{12} = 0b0;
+ let Inst{8-6} = 0b100;
+ let Inst{5} = A;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = 0b0;
+}
+
+multiclass t2VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
+ def acc : t2VADDLV<"vaddlva", suffix,
+ (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
+ "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
+ 0b1, U, pattern>;
+ def no_acc : t2VADDLV<"vaddlv", suffix,
+ (ins MQPR:$Qm), "",
+ 0b0, U, pattern>;
+}
+
+
+defm VADDLVs32 : t2VADDLV_A<"s32", 0b0>;
+defm VADDLVu32 : t2VADDLV_A<"u32", 0b1>;
+
+class t2VMINMAXNMV<string iname, string suffix, bit sz, bit bit_17, bit bit_7,
+ list<dag> pattern=[]>
+ : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm),
+ NoItinerary, iname, suffix, "$RdaSrc, $Qm",
+ "$RdaDest = $RdaSrc", pattern> {
+ bits<3> Qm;
+ bits<4> RdaDest;
+
+ let Inst{28} = sz;
+ let Inst{22-20} = 0b110;
+ let Inst{19-18} = 0b11;
+ let Inst{17} = bit_17;
+ let Inst{16} = 0b0;
+ let Inst{15-12} = RdaDest{3-0};
+ let Inst{8} = 0b1;
+ let Inst{7} = bit_7;
+ let Inst{6-5} = 0b00;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = 0b0;
+
+ let Predicates = [HasMVEFloat];
+}
+
+multiclass t2VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
+ def f32 : t2VMINMAXNMV<iname, "f32", 0b0, 0b1, bit_7, pattern>;
+ def f16 : t2VMINMAXNMV<iname, "f16", 0b1, 0b1, bit_7, pattern>;
+}
+
+defm VMINNMV : t2VMINMAXNMV_fty<"vminnmv", 0b1>;
+defm VMAXNMV : t2VMINMAXNMV_fty<"vmaxnmv", 0b0>;
+
+multiclass t2VMINMAXNMAV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
+ def f32 : t2VMINMAXNMV<iname, "f32", 0b0, 0b0, bit_7, pattern>;
+ def f16 : t2VMINMAXNMV<iname, "f16", 0b1, 0b0, bit_7, pattern>;
+}
+
+defm VMINNMAV : t2VMINMAXNMAV_fty<"vminnmav", 0b1>;
+defm VMAXNMAV : t2VMINMAXNMAV_fty<"vmaxnmav", 0b0>;
+
+class t2VMINMAXV<string iname, string suffix, bit U, bits<2> size,
+ bit bit_17, bit bit_7, list<dag> pattern=[]>
+ : MVE_rDest<(outs rGPR:$RdaDest), (ins rGPR:$RdaSrc, MQPR:$Qm), NoItinerary,
+ iname, suffix, "$RdaSrc, $Qm", "$RdaDest = $RdaSrc", pattern> {
+ bits<3> Qm;
+ bits<4> RdaDest;
+
+ let Inst{28} = U;
+ let Inst{22-20} = 0b110;
+ let Inst{19-18} = size{1-0};
+ let Inst{17} = bit_17;
+ let Inst{16} = 0b0;
+ let Inst{15-12} = RdaDest{3-0};
+ let Inst{8} = 0b1;
+ let Inst{7} = bit_7;
+ let Inst{6-5} = 0b00;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = 0b0;
+}
+
+multiclass t2VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
+ def s8 : t2VMINMAXV<iname, "s8", 0b0, 0b00, 0b1, bit_7>;
+ def s16 : t2VMINMAXV<iname, "s16", 0b0, 0b01, 0b1, bit_7>;
+ def s32 : t2VMINMAXV<iname, "s32", 0b0, 0b10, 0b1, bit_7>;
+ def u8 : t2VMINMAXV<iname, "u8", 0b1, 0b00, 0b1, bit_7>;
+ def u16 : t2VMINMAXV<iname, "u16", 0b1, 0b01, 0b1, bit_7>;
+ def u32 : t2VMINMAXV<iname, "u32", 0b1, 0b10, 0b1, bit_7>;
+}
+
+// Prefixed with MVE to prevent conflict with A57 scheduler.
+defm MVE_VMINV : t2VMINMAXV_ty<"vminv", 0b1>;
+defm MVE_VMAXV : t2VMINMAXV_ty<"vmaxv", 0b0>;
+
+multiclass t2VMINMAXAV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
+ def s8 : t2VMINMAXV<iname, "s8", 0b0, 0b00, 0b0, bit_7>;
+ def s16 : t2VMINMAXV<iname, "s16", 0b0, 0b01, 0b0, bit_7>;
+ def s32 : t2VMINMAXV<iname, "s32", 0b0, 0b10, 0b0, bit_7>;
+}
+
+defm MVE_VMINAV : t2VMINMAXAV_ty<"vminav", 0b1>;
+defm MVE_VMAXAV : t2VMINMAXAV_ty<"vmaxav", 0b0>;
+
+class t2VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
+ bit sz, bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
+ list<dag> pattern=[]>
+ : MVE_rDest<(outs tGPREven:$RdaDest), iops, NoItinerary, iname, suffix,
+ "$RdaDest, $Qn, $Qm", cstr, pattern> {
+ bits<4> RdaDest;
+ bits<3> Qm;
+ bits<3> Qn;
+
+ let Inst{28} = bit_28;
+ let Inst{22-20} = 0b111;
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = sz;
+ let Inst{15-13} = RdaDest{3-1};
+ let Inst{12} = X;
+ let Inst{8} = bit_8;
+ let Inst{7-6} = 0b00;
+ let Inst{5} = A;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = bit_0;
+}
+
+multiclass t2VMLAMLSDAV_X<string iname, string suffix, dag iops, string cstr,
+ bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
+ list<dag> pattern=[]> {
+ def _noexch : t2VMLAMLSDAV<iname, suffix, iops, cstr, sz,
+ bit_28, A, 0b0, bit_8, bit_0, pattern>;
+ def _exch : t2VMLAMLSDAV<iname # "x", suffix, iops, cstr, sz,
+ bit_28, A, 0b1, bit_8, bit_0, pattern>;
+}
+
+multiclass t2VMLAMLSDAV_XA<string iname, string suffix, bit sz, bit bit_28,
+ bit bit_8, bit bit_0, list<dag> pattern=[]> {
+ defm _noacc : t2VMLAMLSDAV_X<iname, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
+ sz, bit_28, 0b0, bit_8, bit_0, pattern>;
+ defm _acc : t2VMLAMLSDAV_X<iname # "a", suffix,
+ (ins tGPREven:$RdaSrc, MQPR:$Qn, MQPR:$Qm),
+ "$RdaDest = $RdaSrc",
+ sz, bit_28, 0b1, bit_8, bit_0, pattern>;
+}
+
+multiclass t2VMLADAV_multi<string suffix, bit sz, bit U, bit bit_8,
+ list<dag> pattern=[]> {
+ defm "" : t2VMLAMLSDAV_XA<"vmladav", suffix, sz, U, bit_8, 0b0, pattern>;
+}
+
+defm VMLADAVs16 : t2VMLADAV_multi<"s16", 0b0, 0b0, 0b0>;
+defm VMLADAVs32 : t2VMLADAV_multi<"s32", 0b1, 0b0, 0b0>;
+defm VMLADAVu16 : t2VMLADAV_multi<"u16", 0b0, 0b1, 0b0>;
+defm VMLADAVu32 : t2VMLADAV_multi<"u32", 0b1, 0b1, 0b0>;
+
+defm VMLADAVs8 : t2VMLADAV_multi<"s8", 0b0, 0b0, 0b1>;
+defm VMLADAVu8 : t2VMLADAV_multi<"u8", 0b0, 0b1, 0b1>;
+
+// vmlav aliases vmladav
+foreach acc = ["_acc", "_noacc"] in {
+ foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32"] in {
+ def : MVEInstAlias<!strconcat("vmlav", !if(!eq(acc, "_acc"), "a", ""),
+ "${vp}.", suffix, "\t$RdaDest, $Qn, $Qm"),
+ (!cast<Instruction>(!strconcat("VMLADAV", suffix, acc, "_noexch")) tGPREven:$RdaDest, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+ }
+}
+
+multiclass t2VMLSDAV_multi<string suffix, bit sz, bit bit_28,
+ list<dag> pattern=[]> {
+ defm "" : t2VMLAMLSDAV_XA<"vmlsdav", suffix, sz, bit_28, 0b0, 0b1, pattern>;
+}
+
+defm t2VMLSDAVs8 : t2VMLSDAV_multi<"s8", 0, 0b1>;
+defm t2VMLSDAVs16 : t2VMLSDAV_multi<"s16", 0, 0b0>;
+defm t2VMLSDAVs32 : t2VMLSDAV_multi<"s32", 1, 0b0>;
+
+// Base class for VMLALDAV and VMLSLDAV, VRMLALDAVH, VRMLSLDAVH
+class t2VMLALDAVBase<string iname, string suffix, dag iops, string cstr, bit sz,
+ bit bit_28, bit A, bit X, bit bit_8, bit bit_0,
+ list<dag> pattern=[]>
+ : MVE_rDest<(outs tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest), iops, NoItinerary,
+ iname, suffix, "$RdaLoDest, $RdaHiDest, $Qn, $Qm", cstr, pattern> {
+ bits<4> RdaLoDest;
+ bits<4> RdaHiDest;
+ bits<3> Qm;
+ bits<3> Qn;
+
+ let Inst{28} = bit_28;
+ let Inst{22-20} = RdaHiDest{3-1};
+ let Inst{19-17} = Qn{2-0};
+ let Inst{16} = sz;
+ let Inst{15-13} = RdaLoDest{3-1};
+ let Inst{12} = X;
+ let Inst{8} = bit_8;
+ let Inst{7-6} = 0b00;
+ let Inst{5} = A;
+ let Inst{3-1} = Qm{2-0};
+ let Inst{0} = bit_0;
+}
+
+multiclass t2VMLALDAVBase_X<string iname, string suffix, dag iops, string cstr,
+ bit sz, bit bit_28, bit A, bit bit_8, bit bit_0,
+ list<dag> pattern=[]> {
+ def _noexch : t2VMLALDAVBase<iname, suffix, iops, cstr, sz,
+ bit_28, A, 0b0, bit_8, bit_0, pattern>;
+ def _exch : t2VMLALDAVBase<iname # "x", suffix, iops, cstr, sz,
+ bit_28, A, 0b1, bit_8, bit_0, pattern>;
+}
+
+multiclass t2VMLALDAVBase_XA<string iname, string suffix, bit sz, bit bit_28,
+ bit bit_8, bit bit_0, list<dag> pattern=[]> {
+ defm _noacc : t2VMLALDAVBase_X<iname, suffix,
+ (ins MQPR:$Qn, MQPR:$Qm), "",
+ sz, bit_28, 0b0, bit_8, bit_0, pattern>;
+ defm _acc : t2VMLALDAVBase_X<iname # "a", suffix,
+ (ins tGPREven:$RdaLoSrc, tGPROdd:$RdaHiSrc, MQPR:$Qn, MQPR:$Qm),
+ "$RdaLoDest = $RdaLoSrc,$RdaHiDest = $RdaHiSrc",
+ sz, bit_28, 0b1, bit_8, bit_0, pattern>;
+}
+
+multiclass t2VRMLALDAVH_multi<string suffix, bit U, list<dag> pattern=[]> {
+ defm "" : t2VMLALDAVBase_XA<"vrmlaldavh", suffix, 0b0, U, 0b1, 0b0, pattern>;
+}
+
+defm t2VRMLALDAVHs32 : t2VRMLALDAVH_multi<"s32", 0>;
+defm t2VRMLALDAVHu32 : t2VRMLALDAVH_multi<"u32", 1>;
+
+// vrmlalvh aliases for vrmlaldavh
+def : MVEInstAlias<"vrmlalvh${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+ (t2VRMLALDAVHs32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+ MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.s32\t$RdaLo, $RdaHi, $Qn, $Qm",
+ (t2VRMLALDAVHs32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+ MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvh${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+ (t2VRMLALDAVHu32_noacc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+ MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+def : MVEInstAlias<"vrmlalvha${vp}.u32\t$RdaLo, $RdaHi, $Qn, $Qm",
+ (t2VRMLALDAVHu32_acc_noexch tGPREven:$RdaLo, tGPROdd:$RdaHi,
+ MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+
+multiclass t2VMLALDAV_multi<string suffix, bit sz, bit U, list<dag> pattern=[]> {
+ defm "" : t2VMLALDAVBase_XA<"vmlaldav", suffix, sz, U, 0b0, 0b0, pattern>;
+}
+
+defm VMLALDAVs16 : t2VMLALDAV_multi<"s16", 0b0, 0b0>;
+defm VMLALDAVs32 : t2VMLALDAV_multi<"s32", 0b1, 0b0>;
+defm VMLALDAVu16 : t2VMLALDAV_multi<"u16", 0b0, 0b1>;
+defm VMLALDAVu32 : t2VMLALDAV_multi<"u32", 0b1, 0b1>;
+
+// vmlalv aliases vmlaldav
+foreach acc = ["_acc", "_noacc"] in {
+ foreach suffix = ["s16", "s32", "u16", "u32"] in {
+ def : MVEInstAlias<!strconcat("vmlalv", !if(!eq(acc, "_acc"), "a", ""),
+ "${vp}.", suffix, "\t$RdaLoDest, $RdaHiDest, $Qn, $Qm"),
+ (!cast<Instruction>(!strconcat("VMLALDAV", suffix, acc, "_noexch"))
+ tGPREven:$RdaLoDest, tGPROdd:$RdaHiDest,
+ MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+ }
+}
+
+multiclass t2VMLSLDAV_multi<string iname, string suffix, bit sz,
+ bit bit_28, list<dag> pattern=[]> {
+ defm "" : t2VMLALDAVBase_XA<iname, suffix, sz, bit_28, 0b0, 0b1, pattern>;
+}
+
+defm t2VMLSLDAVs16 : t2VMLSLDAV_multi<"vmlsldav", "s16", 0b0, 0b0>;
+defm t2VMLSLDAVs32 : t2VMLSLDAV_multi<"vmlsldav", "s32", 0b1, 0b0>;
+defm t2VRMLSLDAVHs32 : t2VMLSLDAV_multi<"vrmlsldavh", "s32", 0b0, 0b1>;
+
// end of mve_rDest instructions
// start of mve_comp instructions
Added: llvm/trunk/test/MC/ARM/mve-reductions-fp.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-reductions-fp.s?rev=363403&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-reductions-fp.s (added)
+++ llvm/trunk/test/MC/ARM/mve-reductions-fp.s Fri Jun 14 07:31:13 2019
@@ -0,0 +1,58 @@
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: FileCheck --check-prefix=ERROR-NOFP < %t %s
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s \
+# RUN: | FileCheck --check-prefix=CHECK %s
+
+# CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vminnmv.f16 lr, q3
+
+# CHECK: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOFP-NOT: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vminnmv.f32 lr, q1
+
+# CHECK: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOFP-NOT: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vminnmav.f16 lr, q0
+
+# CHECK: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vminnmav.f32 lr, q3
+
+# CHECK: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOFP-NOT: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vmaxnmv.f16 lr, q1
+
+# CHECK: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOFP-NOT: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vmaxnmv.f32 r10, q1
+
+# CHECK: vmaxnmav.f16 r0, q6 @ encoding: [0xec,0xfe,0x0c,0x0f]
+# CHECK-NOFP-NOT: vmaxnmav.f16 r0, q6 @ encoding: [0xec,0xfe,0x0c,0x0f]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vmaxnmav.f16 r0, q6
+
+# CHECK: vmaxnmav.f32 lr, q7 @ encoding: [0xec,0xee,0x0e,0xef]
+# CHECK-NOFP-NOT: vmaxnmav.f32 lr, q7 @ encoding: [0xec,0xee,0x0e,0xef]
+# ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
+vmaxnmav.f32 lr, q7
+
+# ----------------------------------------------------------------------
+# The following tests have to go last because of the NOFP-NOT checks inside the
+# VPT block.
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOFP-NOT: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+vpte.i8 eq, q0, q0
+vminnmavt.f32 lr, q3
+vminnmave.f32 lr, q3
Modified: llvm/trunk/test/MC/ARM/mve-reductions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-reductions.s?rev=363403&r1=363402&r2=363403&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-reductions.s (original)
+++ llvm/trunk/test/MC/ARM/mve-reductions.s Fri Jun 14 07:31:13 2019
@@ -1,28 +1,201 @@
-# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s \
-# RUN: | FileCheck --check-prefix=CHECK-NOFP %s
-# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s \
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding < %s 2>%t \
+# RUN: | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
# CHECK: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
-# CHECK-NOFP: vabav.s8 r0, q1, q3 @ encoding: [0x82,0xee,0x07,0x0f]
vabav.s8 r0, q1, q3
# CHECK: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
-# CHECK-NOFP: vabav.s16 r0, q1, q3 @ encoding: [0x92,0xee,0x07,0x0f]
vabav.s16 r0, q1, q3
# CHECK: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
-# CHECK-NOFP: vabav.s32 r0, q1, q3 @ encoding: [0xa2,0xee,0x07,0x0f]
vabav.s32 r0, q1, q3
# CHECK: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
-# CHECK-NOFP: vabav.u8 r0, q1, q3 @ encoding: [0x82,0xfe,0x07,0x0f]
vabav.u8 r0, q1, q3
# CHECK: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
-# CHECK-NOFP: vabav.u16 r0, q1, q3 @ encoding: [0x92,0xfe,0x07,0x0f]
vabav.u16 r0, q1, q3
# CHECK: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
-# CHECK-NOFP: vabav.u32 r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
vabav.u32 r0, q1, q3
+
+# CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
+vaddv.s16 lr, q0
+
+# ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
+vaddv.s16 r1, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vaddvt.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
+# CHECK: vaddve.s16 r0, q6 @ encoding: [0xf5,0xee,0x0c,0x0f]
+vpte.i8 eq, q0, q0
+vaddvt.s16 r0, q6
+vaddve.s16 r0, q6
+
+# CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+vaddva.s16 lr, q0
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+vpte.i8 eq, q0, q0
+vaddvat.s16 lr, q0
+vaddvae.s16 lr, q0
+
+# CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
+vaddlv.s32 r0, r9, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r0, r2, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vaddlv.s32 r1, r3, q2
+
+# CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
+vaddlv.u32 r0, r1, q1
+
+# CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]
+vminv.s8 lr, q0
+
+# CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]
+vminv.s16 lr, q0
+
+# CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]
+vminv.s32 lr, q2
+
+# CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]
+vminv.u8 r0, q0
+
+# CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]
+vminv.u32 r10, q3
+
+# CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]
+vminav.s16 r0, q0
+
+# CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]
+vminav.s8 r0, q1
+
+# CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]
+vminav.s32 lr, q1
+
+# CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]
+vmaxv.s8 lr, q4
+
+# CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]
+vmaxv.s16 lr, q0
+
+# CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]
+vmaxv.s32 r1, q1
+
+# CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]
+vmaxv.u8 r0, q4
+
+# CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]
+vmaxv.u16 r0, q1
+
+# CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]
+vmaxv.u32 r1, q0
+
+# CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]
+vmaxav.s8 lr, q6
+
+# CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]
+vmaxav.s16 r0, q6
+
+# CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
+vmaxav.s32 r10, q7
+
+# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
+vmladav.s16 lr, q0, q7
+
+# CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]
+vmladav.s32 lr, q0, q4
+
+# CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]
+vmladav.u16 lr, q0, q7
+
+# CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]
+vmladav.u32 lr, q0, q0
+
+# CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]
+vmladava.s16 lr, q0, q4
+
+# CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]
+vmladavx.s16 r0, q0, q7
+
+# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
+vmladavax.s16 lr, q0, q7
+
+# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
+vmladav.s8 lr, q3, q0
+
+# CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]
+vmladav.u8 lr, q1, q7
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlaldavh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlaldavh.u32 lr, r1, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r1, r3, q5, q2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+vrmlaldavh.u32 r2, r4, q5, q2
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
+vrmlaldavhax.s32 lr, r1, q3, q0
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]
+vrmlsldavh.s32 lr, r11, q6, q5
+
+# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
+vrmlalvh.s32 lr, r1, q6, q2
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
+vrmlalvh.u32 lr, r1, q5, q2
+
+# CHECK: vrmlalvha.s32 lr, r1, q3, q6 @ encoding: [0x86,0xee,0x2c,0xef]
+vrmlalvha.s32 lr, r1, q3, q6
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]
+vrmlalvha.u32 lr, r1, q7, q1
+
+# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
+vmlsdav.s16 lr, q0, q3
+
+# CHECK: vmlsdav.s32 lr, q2, q6 @ encoding: [0xf5,0xee,0x0d,0xee]
+vmlsdav.s32 lr, q2, q6
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK: vmlsdavaxt.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
+# CHECK: vmlsdavaxe.s16 lr, q1, q4 @ encoding: [0xf2,0xee,0x29,0xfe]
+vpte.i8 eq, q0, q0
+vmlsdavaxt.s16 lr, q1, q4
+vmlsdavaxe.s16 lr, q1, q4
+
+# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
+vmlav.s16 lr, q0, q7
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]
+vmlaldav.s16 lr, r1, q4, q1
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]
+vmlaldav.s32 lr, r11, q4, q1
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]
+vmlalv.s32 r0, r1, q7, q6
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]
+vmlalv.u16 lr, r11, q5, q4
Modified: llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt?rev=363403&r1=363402&r2=363403&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/mve-reductions.txt Fri Jun 14 07:31:13 2019
@@ -25,3 +25,215 @@
[0xa2 0xfe 0x07 0x0f]
# CHECK: vabav.u32 r0, q1, q3
# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+# CHECK: vaddv.s16 lr, q0 @ encoding: [0xf5,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x00,0xef]
+
+# CHECK: vaddva.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vaddvat.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vaddvae.s16 lr, q0 @ encoding: [0xf5,0xee,0x20,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xf5,0xee,0x20,0xef]
+[0xf5,0xee,0x20,0xef]
+
+# CHECK: vaddlv.s32 r0, r9, q2 @ encoding: [0xc9,0xee,0x04,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc9,0xee,0x04,0x0f]
+
+# CHECK: vaddlv.u32 r0, r1, q1 @ encoding: [0x89,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x89,0xfe,0x02,0x0f]
+
+# CHECK: vminnmv.f16 lr, q3 @ encoding: [0xee,0xfe,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x86,0xef]
+
+# CHECK: vminnmv.f32 lr, q1 @ encoding: [0xee,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x82,0xef]
+
+# CHECK: vminnmav.f16 lr, q0 @ encoding: [0xec,0xfe,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xfe,0x80,0xef]
+
+# CHECK: vminnmav.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vminnmavt.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vminnmave.f32 lr, q3 @ encoding: [0xec,0xee,0x86,0xef]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xec,0xee,0x86,0xef]
+[0xec,0xee,0x86,0xef]
+
+# CHECK: vminv.s8 lr, q0 @ encoding: [0xe2,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x80,0xef]
+
+# CHECK: vminv.s16 lr, q0 @ encoding: [0xe6,0xee,0x80,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x80,0xef]
+
+# CHECK: vminv.s32 lr, q2 @ encoding: [0xea,0xee,0x84,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x84,0xef]
+
+# CHECK: vminv.u8 r0, q0 @ encoding: [0xe2,0xfe,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x80,0x0f]
+
+# CHECK: vminv.u32 r10, q3 @ encoding: [0xea,0xfe,0x86,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x86,0xaf]
+
+# CHECK: vminav.s16 r0, q0 @ encoding: [0xe4,0xee,0x80,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x80,0x0f]
+
+# CHECK: vminav.s8 r0, q1 @ encoding: [0xe0,0xee,0x82,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x82,0x0f]
+
+# CHECK: vminav.s32 lr, q1 @ encoding: [0xe8,0xee,0x82,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x82,0xef]
+
+# CHECK: vmaxnmv.f16 lr, q1 @ encoding: [0xee,0xfe,0x02,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xfe,0x02,0xef]
+
+# CHECK: vmaxnmv.f32 r10, q1 @ encoding: [0xee,0xee,0x02,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0xee,0x02,0xaf]
+
+# CHECK: vmaxv.s8 lr, q4 @ encoding: [0xe2,0xee,0x08,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xee,0x08,0xef]
+
+# CHECK: vmaxv.s16 lr, q0 @ encoding: [0xe6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xee,0x00,0xef]
+
+# CHECK: vmaxv.s32 r1, q1 @ encoding: [0xea,0xee,0x02,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xee,0x02,0x1f]
+
+# CHECK: vmaxv.u8 r0, q4 @ encoding: [0xe2,0xfe,0x08,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe2,0xfe,0x08,0x0f]
+
+# CHECK: vmaxv.u16 r0, q1 @ encoding: [0xe6,0xfe,0x02,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe6,0xfe,0x02,0x0f]
+
+# CHECK: vmaxv.u32 r1, q0 @ encoding: [0xea,0xfe,0x00,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xea,0xfe,0x00,0x1f]
+
+# CHECK: vmaxav.s8 lr, q6 @ encoding: [0xe0,0xee,0x0c,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe0,0xee,0x0c,0xef]
+
+# CHECK: vmaxav.s16 r0, q6 @ encoding: [0xe4,0xee,0x0c,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe4,0xee,0x0c,0x0f]
+
+# CHECK: vmaxav.s32 r10, q7 @ encoding: [0xe8,0xee,0x0e,0xaf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xe8,0xee,0x0e,0xaf]
+
+# CHECK: vmlav.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0xee]
+
+# CHECK: vmlav.s32 lr, q0, q4 @ encoding: [0xf1,0xee,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xee,0x08,0xee]
+
+# CHECK: vmlav.u16 lr, q0, q7 @ encoding: [0xf0,0xfe,0x0e,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xfe,0x0e,0xee]
+
+# CHECK: vmlav.u32 lr, q0, q0 @ encoding: [0xf1,0xfe,0x00,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf1,0xfe,0x00,0xee]
+
+# CHECK: vmlava.s16 lr, q0, q4 @ encoding: [0xf0,0xee,0x28,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x28,0xee]
+
+# CHECK: vmladavx.s16 r0, q0, q7 @ encoding: [0xf0,0xee,0x0e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x0e,0x1e]
+
+# CHECK: vmladavax.s16 lr, q0, q7 @ encoding: [0xf0,0xee,0x2e,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x2e,0xfe]
+
+# CHECK: vmlav.s8 lr, q3, q0 @ encoding: [0xf6,0xee,0x00,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf6,0xee,0x00,0xef]
+
+# CHECK: vmlav.u8 lr, q1, q7 @ encoding: [0xf2,0xfe,0x0e,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf2,0xfe,0x0e,0xef]
+
+# CHECK: vrmlalvh.s32 lr, r1, q6, q2 @ encoding: [0x8c,0xee,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8c,0xee,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlalvh.u32 lr, r1, q5, q2 @ encoding: [0x8a,0xfe,0x04,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8a,0xfe,0x04,0xef]
+
+# CHECK: vrmlaldavhax.s32 lr, r1, q3, q0 @ encoding: [0x86,0xee,0x20,0xff]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x86,0xee,0x20,0xff]
+
+# CHECK: vrmlsldavh.s32 lr, r11, q6, q5 @ encoding: [0xdc,0xfe,0x0b,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xdc,0xfe,0x0b,0xee]
+
+# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vrmlalvha.u32 lr, r1, q7, q1 @ encoding: [0x8e,0xfe,0x22,0xef]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8e,0xfe,0x22,0xef]
+
+# CHECK: vmlsdav.s16 lr, q0, q3 @ encoding: [0xf0,0xee,0x07,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xf0,0xee,0x07,0xee]
+
+# CHECK: vmlalv.s16 lr, r1, q4, q1 @ encoding: [0x88,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x88,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 lr, r11, q4, q1 @ encoding: [0xd9,0xee,0x02,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xd9,0xee,0x02,0xee]
+
+# CHECK: vmlalv.s32 r0, r1, q7, q6 @ encoding: [0x8f,0xee,0x0c,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x8f,0xee,0x0c,0x0e]
+
+# CHECK: vmlalv.u16 lr, r11, q5, q4 @ encoding: [0xda,0xfe,0x08,0xee]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xda,0xfe,0x08,0xee]
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