[PATCH] D54296: [RISCV] Lower inline asm constraint A for RISC-V
Lewis Revill via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 13 05:58:58 PDT 2019
lewis-revill updated this revision to Diff 204506.
lewis-revill retitled this revision from "[WIP, RISCV] Lower inline asm constraint A for RISC-V" to "[RISCV] Lower inline asm constraint A for RISC-V".
lewis-revill added a comment.
Herald added subscribers: Jim, benna, psnobl.
Add `Constraint_A` to account for future modifications to `Constraint_m` handling. `Constraint_A` should only ever utilize a single base address without an offset.
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D54296/new/
https://reviews.llvm.org/D54296
Files:
include/llvm/IR/InlineAsm.h
lib/Target/RISCV/RISCVAsmPrinter.cpp
lib/Target/RISCV/RISCVISelDAGToDAG.cpp
lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/RISCV/RISCVISelLowering.h
test/CodeGen/RISCV/inline-asm.ll
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