[PATCH] D63257: [ARM] Select MVE fp add and sub
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 13 05:46:22 PDT 2019
dmgreen created this revision.
dmgreen added reviewers: t.p.northover, simon_tatham, samparker, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.
Same as integer addition, we can add simple floating point MVE addition and subtraction patterns.
Initial code by David Sherwood
https://reviews.llvm.org/D63257
Files:
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
Index: llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
+++ llvm/test/CodeGen/Thumb2/mve-simple-arith.ll
@@ -31,6 +31,26 @@
ret <4 x i32> %0
}
+define arm_aapcs_vfpcc <8 x half> @add_float16_t(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: add_float16_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vadd.f16 q0, q1, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = fadd nnan ninf nsz <8 x half> %src2, %src1
+ ret <8 x half> %0
+}
+
+define arm_aapcs_vfpcc <4 x float> @add_float32_t(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: add_float32_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vadd.f32 q0, q1, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = fadd nnan ninf nsz <4 x float> %src2, %src1
+ ret <4 x float> %0
+}
+
define arm_aapcs_vfpcc <16 x i8> @sub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: sub_int8_t:
@@ -62,3 +82,23 @@
ret <4 x i32> %0
}
+define arm_aapcs_vfpcc <8 x half> @sub_float16_t(<8 x half> %src1, <8 x half> %src2) {
+; CHECK-LABEL: sub_float16_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vsub.f16 q0, q1, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = fsub nnan ninf nsz <8 x half> %src2, %src1
+ ret <8 x half> %0
+}
+
+define arm_aapcs_vfpcc <4 x float> @sub_float32_t(<4 x float> %src1, <4 x float> %src2) {
+; CHECK-LABEL: sub_float32_t:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: vsub.f32 q0, q1, q0
+; CHECK-NEXT: bx lr
+entry:
+ %0 = fsub nnan ninf nsz <4 x float> %src2, %src1
+ ret <4 x float> %0
+}
+
Index: llvm/lib/Target/ARM/ARMInstrMVE.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrMVE.td
+++ llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -4089,9 +4089,23 @@
(v4i32 MQPR:$val2)))>;
}
+multiclass unpred_fp_op_rr<SDPatternOperator opnode, string RegRegOp> {
+ def f16 : Pat<(v8f16 (opnode (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
+ (v8f16 (!cast<Instruction>(RegRegOp#"f16")
+ (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
+ def f32 : Pat<(v4f32 (opnode (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
+ (v4f32 (!cast<Instruction>(RegRegOp#"f32")
+ (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
+}
+
// Arithmetic
let Predicates = [HasMVEInt] in {
defm Pat_VADDt1i : unpred_int_op_rr<add, "VADDt1">;
defm Pat_VSUBt1i : unpred_int_op_rr<sub, "VSUBt1">;
}
+
+let Predicates = [HasMVEFloat] in {
+ defm Pat_VADDfpt1 : unpred_fp_op_rr<fadd, "VADDt1">;
+ defm Pat_VSUBfpt1 : unpred_fp_op_rr<fsub, "VSUBt1">;
+}
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