[PATCH] D63204: [AMDGPU] gfx1010 core wave32 changes

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 204338.
rampitec added a comment.

Rebased. Some of the tests already in the trunk.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63204/new/

https://reviews.llvm.org/D63204

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/AMDGPU.td
  lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AMDGPUInstrInfo.td
  lib/Target/AMDGPU/AMDGPUInstructions.td
  lib/Target/AMDGPU/AMDGPUSubtarget.cpp
  lib/Target/AMDGPU/AMDGPUSubtarget.h
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
  lib/Target/AMDGPU/SIFrameLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInsertSkips.cpp
  lib/Target/AMDGPU/SIInsertWaitcnts.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/SIInstructions.td
  lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  lib/Target/AMDGPU/SILowerControlFlow.cpp
  lib/Target/AMDGPU/SILowerI1Copies.cpp
  lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
  lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  lib/Target/AMDGPU/SIRegisterInfo.h
  lib/Target/AMDGPU/SIRegisterInfo.td
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  lib/Target/AMDGPU/SIWholeQuadMode.cpp
  lib/Target/AMDGPU/SOPInstructions.td
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  lib/Target/AMDGPU/VOP2Instructions.td
  lib/Target/AMDGPU/VOP3Instructions.td
  lib/Target/AMDGPU/VOPCInstructions.td
  lib/Transforms/InstCombine/InstCombineCalls.cpp
  test/CodeGen/AMDGPU/add3.ll
  test/CodeGen/AMDGPU/add_i1.ll
  test/CodeGen/AMDGPU/add_shl.ll
  test/CodeGen/AMDGPU/and_or.ll
  test/CodeGen/AMDGPU/diverge-switch-default.ll
  test/CodeGen/AMDGPU/hazard-in-bundle.mir
  test/CodeGen/AMDGPU/huge-private-buffer.ll
  test/CodeGen/AMDGPU/insert-skip-from-vcc.mir
  test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll
  test/CodeGen/AMDGPU/loop_break.ll
  test/CodeGen/AMDGPU/mubuf-legalize-operands.mir
  test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
  test/CodeGen/AMDGPU/multilevel-break.ll
  test/CodeGen/AMDGPU/nested-loop-conditions.ll
  test/CodeGen/AMDGPU/or3.ll
  test/CodeGen/AMDGPU/regbank-reassign.mir
  test/CodeGen/AMDGPU/shl_add.ll
  test/CodeGen/AMDGPU/shl_or.ll
  test/CodeGen/AMDGPU/si-annotate-cf-unreachable.ll
  test/CodeGen/AMDGPU/si-annotatecfg-multiple-backedges.ll
  test/CodeGen/AMDGPU/sub_i1.ll
  test/CodeGen/AMDGPU/wave32.ll
  test/CodeGen/AMDGPU/xor3.ll
  test/CodeGen/AMDGPU/xor_add.ll
  test/MC/AMDGPU/gfx10-constant-bus.s
  test/MC/AMDGPU/wave32.s
  test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt
  test/MC/Disassembler/AMDGPU/wave32.txt
  test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
  test/Verifier/AMDGPU/intrinsic-immarg.ll

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