[llvm] r363168 - AMDGPU/GlobalISel: Fix using illegal situations in tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 12 07:23:28 PDT 2019
Author: arsenm
Date: Wed Jun 12 07:23:28 2019
New Revision: 363168
URL: http://llvm.org/viewvc/llvm-project?rev=363168&view=rev
Log:
AMDGPU/GlobalISel: Fix using illegal situations in tests
These were using illegal copies as the side effecting use, so make
them legal.
Modified:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir?rev=363168&r1=363167&r2=363168&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir Wed Jun 12 07:23:28 2019
@@ -36,12 +36,12 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $sgpr0
%2:_(s32) = COPY $sgpr1
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
@@ -58,12 +58,12 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr4
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
@@ -80,12 +80,12 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $sgpr4
%2:_(s32) = COPY $vgpr0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
@@ -102,12 +102,12 @@ body: |
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $vgpr1
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
@@ -123,12 +123,12 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr4
; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $sgpr4
%2:_(s32) = COPY $vgpr0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
@@ -144,12 +144,12 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
- ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(s32) = COPY $vgpr0
%2:_(s32) = COPY $sgpr0
%3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
- $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
+ $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
...
---
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir?rev=363168&r1=363167&r2=363168&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir Wed Jun 12 07:23:28 2019
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: phi_s32_ss_sbranch
@@ -74,7 +75,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -96,7 +97,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -124,7 +125,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -146,7 +147,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -174,7 +175,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -196,7 +197,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -273,7 +274,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -295,7 +296,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -323,7 +324,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -345,7 +346,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -373,7 +374,7 @@ body: |
; CHECK: G_BR %bb.2
; CHECK: bb.2:
; CHECK: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[COPY]](s32), %bb.0, [[COPY3]](s32), %bb.1
- ; CHECK: $sgpr0 = COPY [[PHI]](s32)
+ ; CHECK: $vgpr0 = COPY [[PHI]](s32)
; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
bb.0:
successors: %bb.1, %bb.2
@@ -395,7 +396,7 @@ body: |
bb.2:
%6:_(s32) = G_PHI %0, %bb.0, %5, %bb.1
- $sgpr0 = COPY %6
+ $vgpr0 = COPY %6
S_SETPC_B64 undef $sgpr30_sgpr31
...
@@ -898,10 +899,6 @@ body: |
...
-
-
-
-
---
name: phi_s1_vcc_s_sbranch
legalized: true
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