[llvm] r362968 - [RISCV] Replace map with set in getReqFeatures

[Sameer AbuAsal via llvm-commits]

Author: sabuasal
Date: Mon Jun 10 10:15:45 2019
New Revision: 362968

URL: http://llvm.org/viewvc/llvm-project?rev=362968&view=rev
Log:
 [RISCV] Replace map with set in getReqFeatures

Summary:
Use a set in getReqFeatures() in RISCVCompressInstEmitter instead of a map
because the index we save is not needed.

This also fixes bug 41666.

Reviewers: llvm-commits, apazos, asb, nickdesaulniers

Reviewed By: asb

Subscribers: Jim, nickdesaulniers, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61412

Modified:
    llvm/trunk/utils/TableGen/RISCVCompressInstEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RISCVCompressInstEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RISCVCompressInstEmitter.cpp?rev=362968&r1=362967&r2=362968&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RISCVCompressInstEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RISCVCompressInstEmitter.cpp Mon Jun 10 10:15:45 2019
@@ -64,6 +64,7 @@
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
+#include <set>
 #include <vector>
 using namespace llvm;
 
@@ -474,7 +475,7 @@ void RISCVCompressInstEmitter::evaluateC
                                          SourceOperandMap, DestOperandMap));
 }
 
-static void getReqFeatures(std::map<StringRef, int> &FeaturesMap,
+static void getReqFeatures(std::set<StringRef> &FeaturesSet,
                            const std::vector<Record *> &ReqFeatures) {
   for (auto &R : ReqFeatures) {
     StringRef AsmCondString = R->getValueAsString("AssemblerCondString");
@@ -483,11 +484,9 @@ static void getReqFeatures(std::map<Stri
     SmallVector<StringRef, 4> Ops;
     SplitString(AsmCondString, Ops, ",");
     assert(!Ops.empty() && "AssemblerCondString cannot be empty");
-
     for (auto &Op : Ops) {
       assert(!Op.empty() && "Empty operator");
-      if (FeaturesMap.find(Op) == FeaturesMap.end())
-        FeaturesMap[Op] = FeaturesMap.size();
+      FeaturesSet.insert(Op);
     }
   }
 }
@@ -620,9 +619,9 @@ void RISCVCompressInstEmitter::emitCompr
       CaseStream.indent(4) << "case " + Namespace + "::" + CurOp + ": {\n";
     }
 
-    std::map<StringRef, int> FeaturesMap;
+    std::set<StringRef> FeaturesSet;
     // Add CompressPat required features.
-    getReqFeatures(FeaturesMap, CompressPat.PatReqFeatures);
+    getReqFeatures(FeaturesSet, CompressPat.PatReqFeatures);
 
     // Add Dest instruction required features.
     std::vector<Record *> ReqFeatures;
@@ -630,11 +629,10 @@ void RISCVCompressInstEmitter::emitCompr
     copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) {
       return R->getValueAsBit("AssemblerMatcherPredicate");
     });
-    getReqFeatures(FeaturesMap, ReqFeatures);
+    getReqFeatures(FeaturesSet, ReqFeatures);
 
     // Emit checks for all required features.
-    for (auto &F : FeaturesMap) {
-      StringRef Op = F.first;
+    for (auto &Op : FeaturesSet) {
       if (Op[0] == '!')
         CondStream.indent(6) << ("!STI.getFeatureBits()[" + Namespace +
                                  "::" + Op.substr(1) + "]")