[llvm] r362974 - [PowerPC][HTM]Fix $zero is not a GPRC register for builtin_ttest

[Jinsong Ji via llvm-commits]

Author: jsji
Date: Mon Jun 10 12:04:14 2019
New Revision: 362974

URL: http://llvm.org/viewvc/llvm-project?rev=362974&view=rev
Log:
[PowerPC][HTM]Fix $zero is not a GPRC register for builtin_ttest

This was found during HTM cleanup.
Adding a test for builtin_ttest would expose following issue.

*** Bad machine code: Illegal physical register for instruction ***
 - function:    test10
 - basic block: %bb.0 entry (0xf0e57497b58)
 - instruction: %5:crrc0 = TABORTWCI 0, $zero, 0
 - operand 2:   $zero
  $zero is not a GPRC register.
LLVM ERROR: Found 1 machine code errors.

Differential Revision: https://reviews.llvm.org/D63079

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td
    llvm/trunk/test/CodeGen/PowerPC/htm.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td?rev=362974&r1=362973&r2=362974&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrHTM.td Mon Jun 10 12:04:14 2019
@@ -166,6 +166,6 @@ def : Pat<(int_ppc_tsuspend),
           (TSR 0)>;
 
 def : Pat<(i64 (int_ppc_ttest)),
-          (RLDICL (i64 (COPY (TABORTWCI 0, ZERO, 0))), 36, 28)>;
+          (RLDICL (i64 (COPY (TABORTWCI 0, (LI 0), 0))), 36, 28)>;
 
 } // [HasHTM]

Modified: llvm/trunk/test/CodeGen/PowerPC/htm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/htm.ll?rev=362974&r1=362973&r2=362974&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/htm.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/htm.ll Mon Jun 10 12:04:14 2019
@@ -57,16 +57,19 @@ entry:
   %0 = tail call i32 @llvm.ppc.tendall()
   %1 = tail call i32 @llvm.ppc.tresume()
   %2 = tail call i32 @llvm.ppc.tsuspend()
+  %3 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test4
 ; CHECK: tend. 1
 ; CHECK: tsr.  1
 ; CHECK: tsr.  0
+; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
 declare i32 @llvm.ppc.tendall()
 declare i32 @llvm.ppc.tresume()
 declare i32 @llvm.ppc.tsuspend()
+declare i64 @llvm.ppc.ttest()
 
 
 define void @test5(i64 %v) {