[PATCH] D60704: [ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR.

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL362942: [ARM] Disallow PC, and optionally SP, in VMOVRH and VMOVHR. (authored by statham, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D60704?vs=203822&id=203825#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D60704/new/

https://reviews.llvm.org/D60704

Files:
  llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
  llvm/trunk/test/MC/ARM/vmovhr.s


Index: llvm/trunk/test/MC/ARM/vmovhr.s
===================================================================
--- llvm/trunk/test/MC/ARM/vmovhr.s
+++ llvm/trunk/test/MC/ARM/vmovhr.s
@@ -0,0 +1,24 @@
+// RUN: not llvm-mc -triple=thumbv8.2a-none-eabi -mattr=+fp-armv8,+fullfp16 -show-encoding < %s 2>%t \
+// RUN:   | FileCheck %s
+// RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vmov.f16 r0, s13 @ encoding: [0x16,0xee,0x90,0x09]
+vmov.f16 r0, s13
+
+# CHECK: vmov.f16 s21, r1 @ encoding: [0x0a,0xee,0x90,0x19]
+vmov.f16 s21, r1
+
+# CHECK: vmov.f16 s2, sp @ encoding: [0x01,0xee,0x10,0xd9]
+vmov.f16 s2, sp
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR: operand must be a register in range [r0, r14]
+vmov.f16 s3, pc
+
+# CHECK: vmov.f16 sp, s5 @ encoding: [0x12,0xee,0x90,0xd9]
+vmov.f16 sp, s5
+
+# ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
+# ERROR: operand must be a register in range [r0, r14]
+vmov.f16 pc, s8
+
Index: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
@@ -1246,9 +1246,9 @@
 
 // Move H->R, clearing top 16 bits
 def VMOVRH : AVConv2I<0b11100001, 0b1001,
-                      (outs GPR:$Rt), (ins HPR:$Sn),
+                      (outs rGPR:$Rt), (ins HPR:$Sn),
                       IIC_fpMOVSI, "vmov", ".f16\t$Rt, $Sn",
-                      [(set GPR:$Rt, (arm_vmovrh HPR:$Sn))]>,
+                      [(set rGPR:$Rt, (arm_vmovrh HPR:$Sn))]>,
              Requires<[HasFPRegs16]>,
              Sched<[WriteFPMOV]> {
   // Instruction operands.
@@ -1268,9 +1268,9 @@
 
 // Move R->H, clearing top 16 bits
 def VMOVHR : AVConv4I<0b11100000, 0b1001,
-                      (outs HPR:$Sn), (ins GPR:$Rt),
+                      (outs HPR:$Sn), (ins rGPR:$Rt),
                       IIC_fpMOVIS, "vmov", ".f16\t$Sn, $Rt",
-                      [(set HPR:$Sn, (arm_vmovhr GPR:$Rt))]>,
+                      [(set HPR:$Sn, (arm_vmovhr rGPR:$Rt))]>,
              Requires<[HasFPRegs16]>,
              Sched<[WriteFPMOV]> {
   // Instruction operands.


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