[llvm] r362886 - [X86][Codegen] Add missed pattern that may be a lea+neg

[Roman Lebedev via llvm-commits]

On Sat, Jun 8, 2019 at 11:35 PM Craig Topper <craig.topper at gmail.com> wrote:
>
>
>
> On Sat, Jun 8, 2019 at 12:34 PM Roman Lebedev via llvm-commits <llvm-commits at lists.llvm.org> wrote:
>>
>> Author: lebedevri
>> Date: Sat Jun  8 12:38:14 2019
>> New Revision: 362886
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=362886&view=rev
>> Log:
>> [X86][Codegen] Add missed pattern that may be a lea+neg
Apologies, that should of course have been [NFC]

>>
>> Added:
>>     llvm/trunk/test/CodeGen/X86/neg-of-3ops-lea.ll
>>
>> Added: llvm/trunk/test/CodeGen/X86/neg-of-3ops-lea.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/neg-of-3ops-lea.ll?rev=362886&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/neg-of-3ops-lea.ll (added)
>> +++ llvm/trunk/test/CodeGen/X86/neg-of-3ops-lea.ll Sat Jun  8 12:38:14 2019
>> @@ -0,0 +1,86 @@
>> +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
>> +; RUN: llc < %s -mtriple=i686--   -mattr=+slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,X86,SLOW,SLOW-X86
>> +; RUN: llc < %s -mtriple=i686--   -mattr=-slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,X86,FAST,FAST-X86
>> +; RUN: llc < %s -mtriple=x86_64-- -mattr=+slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,X64,SLOW,SLOW-X64
>> +; RUN: llc < %s -mtriple=x86_64-- -mattr=-slow-3ops-lea | FileCheck %s -check-prefixes=CHECK,X64,FAST,FAST-X64
>> +
>> +; )32-a)-b  -->  32-(a+b)  -->  -(a+b)+32  -->  -((a+b)-32)  ->  -(a+b+(-32))
>
>
> I think the first paren is backwards.
Yes, indeed, thanks.

>>
>> +
>> +define i32 @t0(i32 %a, i32 %b) {
>> +; X86-LABEL: t0:
>> +; X86:       # %bb.0:
>> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    addl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    movl $32, %eax
>> +; X86-NEXT:    subl %ecx, %eax
>> +; X86-NEXT:    retl
>> +;
>> +; X64-LABEL: t0:
>> +; X64:       # %bb.0:
>> +; X64-NEXT:    addl %esi, %edi
>> +; X64-NEXT:    movl $32, %eax
>> +; X64-NEXT:    subl %edi, %eax
>> +; X64-NEXT:    retq
>> +  %t0 = sub i32 32, %a
>> +  %r = sub i32 %t0, %b
>> +  ret i32 %r
>> +}
>> +define i32 @t1(i32 %a, i32 %b) {
>> +; X86-LABEL: t1:
>> +; X86:       # %bb.0:
>> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    addl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    movl $32, %eax
>> +; X86-NEXT:    subl %ecx, %eax
>> +; X86-NEXT:    retl
>> +;
>> +; X64-LABEL: t1:
>> +; X64:       # %bb.0:
>> +; X64-NEXT:    addl %esi, %edi
>> +; X64-NEXT:    movl $32, %eax
>> +; X64-NEXT:    subl %edi, %eax
>> +; X64-NEXT:    retq
>> +  %t0 = add i32 %a, %b
>> +  %r = sub i32 32, %t0
>> +  ret i32 %r
>> +}
>> +define i32 @t2(i32 %a, i32 %b) {
>> +; X86-LABEL: t2:
>> +; X86:       # %bb.0:
>> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    addl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    movl $32, %eax
>> +; X86-NEXT:    subl %ecx, %eax
>> +; X86-NEXT:    retl
>> +;
>> +; X64-LABEL: t2:
>> +; X64:       # %bb.0:
>> +; X64-NEXT:    addl %esi, %edi
>> +; X64-NEXT:    movl $32, %eax
>> +; X64-NEXT:    subl %edi, %eax
>> +; X64-NEXT:    retq
>> +  %t0 = add i32 %a, %b
>> +  %t1 = sub i32 0, %t0
>> +  %r = add i32 %t1, 32
>> +  ret i32 %r
>> +}
>> +define i32 @t3(i32 %a, i32 %b) {
>> +; X86-LABEL: t3:
>> +; X86:       # %bb.0:
>> +; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    addl {{[0-9]+}}(%esp), %ecx
>> +; X86-NEXT:    movl $32, %eax
>> +; X86-NEXT:    subl %ecx, %eax
>> +; X86-NEXT:    retl
>> +;
>> +; X64-LABEL: t3:
>> +; X64:       # %bb.0:
>> +; X64-NEXT:    addl %esi, %edi
>> +; X64-NEXT:    movl $32, %eax
>> +; X64-NEXT:    subl %edi, %eax
>> +; X64-NEXT:    retq
>> +  %t0 = add i32 %a, %b
>> +  %t1 = sub i32 %t0, 32
>> +  %r = sub i32 0, %t1
>> +  ret i32 %r
>> +}
>>
>>
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>
> --
> ~Craig