[PATCH] D63028: [InstCombine] Add tests for missing fold icmp pred (and X, (sh signbit, Y)), 0.

[Huihui Zhang via Phabricator via llvm-commits]

huihuiz created this revision.
huihuiz added reviewers: lebedev.ri, efriedma, spatel, craig.topper.
Herald added a project: LLVM.
huihuiz added a comment.

split from D62818 <https://reviews.llvm.org/D62818>


Expect to fold:

  (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0
  (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0


Repository:
  rL LLVM

https://reviews.llvm.org/D63028

Files:
  test/Transforms/InstCombine/icmp-signbit-shift-and.ll


Index: test/Transforms/InstCombine/icmp-signbit-shift-and.ll
===================================================================
--- /dev/null
+++ test/Transforms/InstCombine/icmp-signbit-shift-and.ll
@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+
+; FIXME: expect (X & (signbit l>> Y)) ==/!= 0 -> (X << Y) >=/< 0
+define i1 @signbit-lshr-and(i32 %x, i32 %y) {
+; CHECK-LABEL: @signbit-lshr-and(
+; CHECK-NEXT:    [[LSHR:%.*]] = lshr i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[LSHR]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %lshr = lshr i32 -2147483648, %y
+  %and = and i32 %lshr, %x
+  %r = icmp ne i32 %and, 0
+  ret i1 %r
+}
+
+; FIXME: expect (X & (signbit << Y)) ==/!= 0 -> (X l>> Y) >=/< 0
+define i1 @signbit-shl-and(i32 %x, i32 %y) {
+; CHECK-LABEL: @signbit-shl-and(
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 -2147483648, [[Y:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %shl = shl i32 -2147483648, %y
+  %and = and i32 %shl, %x
+  %r = icmp eq i32 %and, 0
+  ret i1 %r
+}
+


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