[llvm] r362780 - [AArch64][AsmParser] error on unexpected SVE predicate type suffix
Cullen Rhodes via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 7 01:46:56 PDT 2019
Author: c-rhodes
Date: Fri Jun 7 01:46:56 2019
New Revision: 362780
URL: http://llvm.org/viewvc/llvm-project?rev=362780&view=rev
Log:
[AArch64][AsmParser] error on unexpected SVE predicate type suffix
Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:
faddv h0, p0.q, z1.h
This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:
.text
<stdin>:1:13: error: not expecting size suffix
cmpne p1.s, p0.b/z, z2.s, 0
^
A similar issue for SVE vector registers was fixed in:
https://reviews.llvm.org/D59636
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62942
Modified:
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/test/MC/AArch64/SVE/andv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/clasta-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/clastb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/cntp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/compact-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/decp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/eorv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fadda-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/faddv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fmaxv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fminnmv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/fminv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/incp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/lasta-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/lastb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/orv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/pfirst-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/pnext-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/ptest-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/saddv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sel-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/smaxv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sminv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/splice-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqdecp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/sqincp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uaddv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/umaxv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uminv-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqdecp-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/uqincp-diagnostics.s
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Fri Jun 7 01:46:56 2019
@@ -1081,8 +1081,7 @@ public:
if (Kind != k_Register || Reg.Kind != RegKind::SVEPredicateVector)
return DiagnosticPredicateTy::NoMatch;
- if (isSVEVectorReg<Class>() &&
- (ElementWidth == 0 || Reg.ElementWidth == ElementWidth))
+ if (isSVEVectorReg<Class>() && (Reg.ElementWidth == ElementWidth))
return DiagnosticPredicateTy::Match;
return DiagnosticPredicateTy::NearMatch;
Modified: llvm/trunk/test/MC/AArch64/SVE/andv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/andv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/andv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/andv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ andv h0, p8, z31.h
// CHECK-NEXT: andv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+andv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: andv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+andv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: andv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/clasta-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/clasta-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/clasta-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/clasta-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -9,6 +9,16 @@ clasta w0, p8, w0, z31.b
// CHECK-NEXT: clasta w0, p8, w0, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+clasta w0, p7.b, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: clasta w0, p7.b, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+clasta w0, p7.q, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: clasta w0, p7.q, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Invalid element width
Modified: llvm/trunk/test/MC/AArch64/SVE/clastb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/clastb-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/clastb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/clastb-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -9,6 +9,16 @@ clastb w0, p8, w0, z31.b
// CHECK-NEXT: clastb w0, p8, w0, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+clastb w0, p7.b, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: clastb w0, p7.b, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+clastb w0, p7.q, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: clastb w0, p7.q, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Invalid element width
Modified: llvm/trunk/test/MC/AArch64/SVE/cntp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/cntp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/cntp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/cntp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,7 +5,21 @@ cntp sp
// CHECK-NEXT: cntp sp
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
cntp x0, p15, p0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: cntp x0, p15, p0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cntp x0, p15.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: cntp x0, p15.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cntp x0, p15.q, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: cntp x0, p15.q, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/compact-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/compact-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/compact-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/compact-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -8,6 +8,16 @@ compact z23.d, p8, z13.d
// CHECK-NEXT: compact z23.d, p8, z13.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+compact z23.d, p7.b, z13.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: compact z23.d, p7.b, z13.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+compact z23.d, p7.q, z13.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: compact z23.d, p7.q, z13.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid element widths
Modified: llvm/trunk/test/MC/AArch64/SVE/decp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/decp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/decp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/decp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -37,6 +37,16 @@ decp x0, p0.q
// CHECK-NEXT: decp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+decp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: decp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+decp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: decp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/eorv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/eorv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/eorv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/eorv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ eorv h0, p8, z31.h
// CHECK-NEXT: eorv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+eorv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: eorv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eorv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: eorv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/fadda-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fadda-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fadda-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fadda-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -10,16 +10,31 @@ fadda h0, p7, h1, z31.h
// CHECK-NEXT: fadda h0, p7, h1, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fadda v0.8h, p7, v0.8h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
fadda h0, p8, h0, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fadda h0, p8, h0, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-fadda v0.8h, p7, v0.8h, z31.h
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-// CHECK-NEXT: fadda v0.8h, p7, v0.8h, z31.h
+fadda h0, p7.b, h0, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fadda h0, p7.b, h0, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fadda h0, p7.q, h0, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fadda h0, p7.q, h0, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/faddv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/faddv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/faddv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/faddv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,11 +5,25 @@ faddv b0, p7, z31.b
// CHECK-NEXT: faddv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
faddv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: faddv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+faddv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: faddv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+faddv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: faddv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Result must be a valid FP register.
Modified: llvm/trunk/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fmaxnmv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,11 +5,25 @@ fmaxnmv b0, p7, z31.b
// CHECK-NEXT: fmaxnmv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
fmaxnmv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxnmv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fmaxnmv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxnmv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxnmv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxnmv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Result must be a valid FP register.
Modified: llvm/trunk/test/MC/AArch64/SVE/fmaxv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fmaxv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fmaxv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fmaxv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,11 +5,25 @@ fmaxv b0, p7, z31.b
// CHECK-NEXT: fmaxv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
fmaxv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fmaxv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fmaxv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fmaxv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Result must be a valid FP register.
Modified: llvm/trunk/test/MC/AArch64/SVE/fminnmv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fminnmv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fminnmv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fminnmv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,11 +5,25 @@ fminnmv b0, p7, z31.b
// CHECK-NEXT: fminnmv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
fminnmv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminnmv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fminnmv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminnmv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminnmv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminnmv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Result must be a valid FP register.
Modified: llvm/trunk/test/MC/AArch64/SVE/fminv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/fminv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/fminv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/fminv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -5,11 +5,26 @@ fminv b0, p7, z31.b
// CHECK-NEXT: fminv b0, p7, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
+
fminv h0, p8, z31.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+fminv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+fminv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: fminv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Result must be a valid FP register.
Modified: llvm/trunk/test/MC/AArch64/SVE/incp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/incp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/incp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/incp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -37,6 +37,16 @@ incp x0, p0.q
// CHECK-NEXT: incp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+incp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: incp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+incp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: incp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/lasta-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lasta-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lasta-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lasta-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -9,6 +9,16 @@ lasta w0, p8, z31.b
// CHECK-NEXT: lasta w0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+lasta w0, p7.b, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: lasta w0, p7.b, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lasta w0, p7.q, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: lasta w0, p7.q, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Invalid element width
Modified: llvm/trunk/test/MC/AArch64/SVE/lastb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lastb-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lastb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lastb-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -9,6 +9,16 @@ lastb w0, p8, z31.b
// CHECK-NEXT: lastb w0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+lastb w0, p7.b, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: lastb w0, p7.b, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+lastb w0, p7.q, w0, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: lastb w0, p7.q, w0, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Invalid element width
Modified: llvm/trunk/test/MC/AArch64/SVE/orv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/orv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/orv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/orv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ orv h0, p8, z31.h
// CHECK-NEXT: orv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+orv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: orv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: orv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/pfirst-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/pfirst-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/pfirst-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/pfirst-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -2,13 +2,33 @@
// ------------------------------------------------------------------------- //
-// Only .b is supported
+// Invalid predicate
pfirst p0.h, p15, p0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: pfirst p0.h, p15, p0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+pfirst p0.b, p15/z, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pfirst p0.b, p15/z, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pfirst p0.b, p15/m, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: pfirst p0.b, p15/m, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pfirst p0.b, p15.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: pfirst p0.b, p15.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pfirst p0.b, p15.q, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: pfirst p0.b, p15.q, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// ------------------------------------------------------------------------- //
// Tied operands must match
Modified: llvm/trunk/test/MC/AArch64/SVE/pnext-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/pnext-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/pnext-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/pnext-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -2,6 +2,20 @@
// ------------------------------------------------------------------------- //
+// Unexpected type suffix
+
+pnext p0.b, p15.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: pnext p0.b, p15.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+pnext p0.b, p15.q, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
+// CHECK-NEXT: pnext p0.b, p15.q, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
// Tied operands must match
pnext p0.b, p15, p1.b
Modified: llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/prfb-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -122,13 +122,23 @@ prfb #0, p0, [z0.d, #32]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
prfb #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfb #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+prfb #0, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfb #0, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+prfb #0, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfb #0, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/prfd-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -108,13 +108,23 @@ prfd #0, p0, [z0.d, #3]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
prfd #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfd #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+prfd #0, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfd #0, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+prfd #0, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfd #0, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/prfh-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -147,13 +147,23 @@ prfh #0, p0, [z0.d, #3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
prfh #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfh #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+prfh #0, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfh #0, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+prfh #0, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfh #0, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/prfw-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -148,13 +148,23 @@ prfw #0, p0, [z0.d, #3]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
prfw #0, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: prfw #0, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+prfw #0, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfw #0, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+prfw #0, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: prfw #0, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/ptest-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/ptest-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/ptest-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/ptest-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -2,9 +2,19 @@
// ------------------------------------------------------------------------- //
-// Only .b is supported
+// Invalid predicate
ptest p15, p15.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
// CHECK-NEXT: ptest p15, p15.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ptest p15.b, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: ptest p15.b, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ptest p15.q, p15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: ptest p15.q, p15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/saddv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/saddv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/saddv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/saddv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ saddv d0, p8, z31.b
// CHECK-NEXT: saddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+saddv d0, p7.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: saddv d0, p7.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+saddv d0, p7.q, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: saddv d0, p7.q, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/sel-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sel-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sel-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sel-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -1,5 +1,28 @@
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
+// ------------------------------------------------------------------------- //
+// Invalid predicate operand
+
+sel z0.b, p0.b, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sel z0.b, p0.b, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sel z0.b, p0.q, z0.b, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sel z0.b, p0.q, z0.b, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sel p0.b, p0.b, p0.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sel p0.b, p0.b, p0.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sel p0.b, p0.q, p0.b, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sel p0.b, p0.q, p0.b, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/smaxv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/smaxv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/smaxv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/smaxv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ smaxv h0, p8, z31.h
// CHECK-NEXT: smaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+smaxv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: smaxv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+smaxv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: smaxv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/sminv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sminv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sminv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sminv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ sminv h0, p8, z31.h
// CHECK-NEXT: sminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sminv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: sminv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sminv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: sminv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/splice-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/splice-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/splice-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/splice-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -26,6 +26,16 @@ splice z0.b, p8, z0.b, z1.b
// CHECK-NEXT: splice z0.b, p8, z0.b, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+splice z0.b, p7.b, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: splice z0.b, p7.b, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+splice z0.b, p7.q, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: splice z0.b, p7.q, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/sqdecp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqdecp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqdecp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqdecp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -52,6 +52,16 @@ sqdecp x0, p0.q
// CHECK-NEXT: sqdecp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqdecp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sqdecp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdecp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sqdecp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/sqincp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/sqincp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/sqincp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/sqincp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -47,6 +47,16 @@ uqdecp x0, p0.q
// CHECK-NEXT: uqdecp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+sqincp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sqincp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqincp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: sqincp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1b-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -44,7 +44,7 @@ st1b z27.d, p1, [x12, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
-// Restricted predicate has range [0, 7].
+// Invalid predicate
st1b z12.b, p8, [x27, #6, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -66,6 +66,16 @@ st1b z14.d, p8, [x6, #5, MUL VL]
// CHECK-NEXT: st1b z14.d, p8, [x6, #5, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st1b z14.d, p7.b, [x6, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1b z14.d, p7.b, [x6, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1b z14.d, p7.q, [x6, #5, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1b z14.d, p7.q, [x6, #5, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list
Modified: llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1d-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -15,13 +15,23 @@ st1d z16.d, p4, [x2, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
-// Restricted predicate has range [0, 7].
+// Invalid predicate
st1d z12.d, p8, [x4, #14, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st1d z12.d, p7.b, [x4, #14, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1d z12.d, p7.b, [x4, #14, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1d z12.d, p7.q, [x4, #14, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1d z12.d, p7.q, [x4, #14, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list
Modified: llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1h-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -34,7 +34,7 @@ st1h z24.d, p3, [x16, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
-// Restricted predicate has range [0, 7].
+// Invalid predicate
st1h z15.h, p8, [x0, #8, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -51,6 +51,16 @@ st1h z15.d, p8, [x0, #8, MUL VL]
// CHECK-NEXT: st1h z15.d, p8, [x0, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st1h z15.d, p7.b, [x0, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1h z15.d, p7.b, [x0, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1h z15.d, p7.b, [x0, #8, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1h z15.d, p7.b, [x0, #8, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list
Modified: llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st1w-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -27,7 +27,7 @@ st1w z10.d, p5, [x26, #8, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
-// Restricted predicate has range [0, 7].
+// Invalid predicate
st1w z1.s, p8, [x3, #1, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -39,6 +39,16 @@ st1w z12.d, p8, [x26, #3, MUL VL]
// CHECK-NEXT: st1w z12.d, p8, [x26, #3, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st1w z12.d, p7.b, [x26, #3, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1w z12.d, p7.b, [x26, #3, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1w z12.d, p7.q, [x26, #3, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1w z12.d, p7.q, [x26, #3, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list
Modified: llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st2b-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -54,13 +54,23 @@ st2b { z0.b, z1.b }, p0, [x0, w0, uxtw]
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2b {z2.b, z3.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st2b {z2.b, z3.b}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2b {z2.b, z3.b}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2b {z2.b, z3.b}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2b {z2.b, z3.b}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st2d-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st2d { z0.d, z1.d }, p0, [x0, w0, uxtw]
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2d {z2.d, z3.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st2d {z2.d, z3.d}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2d {z2.d, z3.d}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2d {z2.d, z3.d}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2d {z2.d, z3.d}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st2h-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st2h { z0.h, z1.h }, p0, [x0, w0, uxtw]
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2h {z2.h, z3.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st2h {z2.h, z3.h}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2h {z2.h, z3.h}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2h {z2.h, z3.h}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2h {z2.h, z3.h}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st2w-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st2w { z0.s, z1.s }, p0, [x0, w0, uxtw]
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st2w {z2.s, z3.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st2w {z2.s, z3.s}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2w {z2.s, z3.s}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st2w {z2.s, z3.s}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st2w {z2.s, z3.s}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st3b-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -54,13 +54,23 @@ st3b { z0.b, z1.b, z2.b }, p0, [x0, w0,
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st3b {z2.b, z3.b, z4.b}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3b {z2.b, z3.b, z4.b}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3b {z2.b, z3.b, z4.b}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st3d-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st3d { z0.d, z1.d, z2.d }, p0, [x0, w0,
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st3d {z2.d, z3.d, z4.d}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3d {z2.d, z3.d, z4.d}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3d {z2.d, z3.d, z4.d}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st3h-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st3h { z0.h, z1.h, z2.h }, p0, [x0, w0,
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st3h {z2.h, z3.h, z4.h}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3h {z2.h, z3.h, z4.h}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3h {z2.h, z3.h, z4.h}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st3w-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st3w { z0.s, z1.s, z2.s }, p0, [x0, w0,
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st3w {z2.s, z3.s, z4.s}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st3w {z2.s, z3.s, z4.s}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st3w {z2.s, z3.s, z4.s}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st4b-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -54,13 +54,23 @@ st4b { z0.b, z1.b, z2.b, z3.b }, p0, [x0
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st4b {z2.b, z3.b, z4.b, z5.b}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4b {z2.b, z3.b, z4.b, z5.b}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4b {z2.b, z3.b, z4.b, z5.b}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st4d-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -58,15 +58,24 @@ st4d { z0.d, z1.d, z2.d, z3.d }, p0, [x0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st4d {z2.d, z3.d, z4.d, z5.d}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4d {z2.d, z3.d, z4.d, z5.d}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4d {z2.d, z3.d, z4.d, z5.d}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st4h-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st4h { z0.h, z1.h, z2.h, z3.h }, p0, [x0
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st4h {z2.h, z3.h, z4.h, z5.h}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4h {z2.h, z3.h, z4.h, z5.h}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4h {z2.h, z3.h, z4.h, z5.h}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/st4w-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -59,13 +59,23 @@ st4w { z0.s, z1.s, z2.s, z3.s }, p0, [x0
// --------------------------------------------------------------------------//
-// error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// Invalid predicate
st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p8, [x15, #10, MUL VL]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.b, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st4w {z2.s, z3.s, z4.s, z5.s}, p7.q, [x15, #10, MUL VL]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -34,16 +34,31 @@ stnt1b z0.d, p0, [x0]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
stnt1b z27.b, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: stnt1b z27.b, p8, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-stnt1b z0.h, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
-// CHECK-NEXT: stnt1b z0.h, p0/z, [x0]
+stnt1b z0.b, p0/z, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b z0.b, p0/z, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b z0.b, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1b z0.b, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b z27.b, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1b z27.b, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1b z27.b, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1b z27.b, p7.q, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1d-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -34,7 +34,7 @@ stnt1d z0.s, p0, [x0]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
stnt1d z27.d, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -46,6 +46,21 @@ stnt1d z0.d, p0/z, [x0]
// CHECK-NEXT: stnt1d z0.d, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+stnt1d z0.d, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1d z0.d, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d z0.d, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1d z0.d, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1d z0.d, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1d z0.d, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1h-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -34,7 +34,7 @@ stnt1h z0.d, p0, [x0]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
stnt1h z27.h, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -46,6 +46,21 @@ stnt1h z0.h, p0/z, [x0]
// CHECK-NEXT: stnt1h z0.h, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+stnt1h z0.h, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1h z0.h, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h z0.h, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1h z0.h, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1h z0.h, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1h z0.h, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/stnt1w-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -34,7 +34,7 @@ stnt1w z0.d, p0, [x0]
// --------------------------------------------------------------------------//
-// invalid predicate
+// Invalid predicate
stnt1w z27.s, p8, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
@@ -46,6 +46,21 @@ stnt1w z0.s, p0/z, [x0]
// CHECK-NEXT: stnt1w z0.s, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+stnt1w z0.s, p0/m, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: stnt1w z0.s, p0/m, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w z0.s, p7.b, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1w z0.s, p7.b, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+stnt1w z0.s, p7.q, [x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: stnt1w z0.s, p7.q, [x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Invalid vector list.
Modified: llvm/trunk/test/MC/AArch64/SVE/uaddv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uaddv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uaddv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uaddv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -28,6 +28,17 @@ uaddv d0, p8, z31.b
// CHECK-NEXT: uaddv d0, p8, z31.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uaddv d0, p7.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: uaddv d0, p7.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uaddv d0, p7.q, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: uaddv d0, p7.q, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/umaxv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/umaxv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/umaxv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/umaxv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ umaxv h0, p8, z31.h
// CHECK-NEXT: umaxv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+umaxv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: umaxv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+umaxv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: umaxv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/uminv-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uminv-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uminv-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uminv-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -33,6 +33,17 @@ uminv h0, p8, z31.h
// CHECK-NEXT: uminv h0, p8, z31.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uminv h0, p7.b, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: uminv h0, p7.b, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uminv h0, p7.q, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: uminv h0, p7.q, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/uqdecp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqdecp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqdecp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqdecp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -1,5 +1,15 @@
// RUN: not llvm-mc -triple=aarch64-none-linux-gnu -show-encoding -mattr=+sve 2>&1 < %s | FileCheck %s
+uqdecp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: uqdecp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqdecp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: uqdecp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
Modified: llvm/trunk/test/MC/AArch64/SVE/uqincp-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/uqincp-diagnostics.s?rev=362780&r1=362779&r2=362780&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/uqincp-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/uqincp-diagnostics.s Fri Jun 7 01:46:56 2019
@@ -47,6 +47,16 @@ uqincp x0, p0.q
// CHECK-NEXT: uqincp x0, p0.q
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+uqincp z0.d, p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: uqincp z0.d, p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uqincp z0.d, p0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK-NEXT: uqincp z0.d, p0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
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