[PATCH] D62996: Improve reduction intrinsics by overloading result value.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: RKSimon, arsenm, rnk, greened, aemerson.
Herald added subscribers: javed.absar, wdng.

This patch uses the mechanism from D62995 <https://reviews.llvm.org/D62995> to strengthen the 
definitions of the reduction intrinsics by letting the scalar
result/accumulator type be overloaded from the vector element type.

For example:

  ; The LLVM LangRef specifies that the scalar result must equal the 
  ; vector element type, but this is not checked/enforced by LLVM.
  declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a) 

This patch changes that into:

  declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a) 

Which has the type-constraint more explicit and causes LLVM to check
the result type with the vector element type.


https://reviews.llvm.org/D62996

Files:
  docs/LangRef.rst
  include/llvm/IR/Intrinsics.h
  include/llvm/IR/Intrinsics.td
  lib/IR/Function.cpp
  lib/IR/IRBuilder.cpp
  test/Analysis/CostModel/AArch64/vector-reduce.ll
  test/Analysis/CostModel/X86/reduce-add-widen.ll
  test/Analysis/CostModel/X86/reduce-add.ll
  test/Analysis/CostModel/X86/reduce-and-widen.ll
  test/Analysis/CostModel/X86/reduce-and.ll
  test/Analysis/CostModel/X86/reduce-mul-widen.ll
  test/Analysis/CostModel/X86/reduce-mul.ll
  test/Analysis/CostModel/X86/reduce-or-widen.ll
  test/Analysis/CostModel/X86/reduce-or.ll
  test/Analysis/CostModel/X86/reduce-smax-widen.ll
  test/Analysis/CostModel/X86/reduce-smax.ll
  test/Analysis/CostModel/X86/reduce-smin-widen.ll
  test/Analysis/CostModel/X86/reduce-smin.ll
  test/Analysis/CostModel/X86/reduce-umax-widen.ll
  test/Analysis/CostModel/X86/reduce-umax.ll
  test/Analysis/CostModel/X86/reduce-umin-widen.ll
  test/Analysis/CostModel/X86/reduce-umin.ll
  test/Analysis/CostModel/X86/reduce-xor-widen.ll
  test/Analysis/CostModel/X86/reduce-xor.ll
  test/CodeGen/AArch64/aarch64-addv.ll
  test/CodeGen/AArch64/aarch64-minmaxv.ll
  test/CodeGen/AArch64/arm64-vabs.ll
  test/CodeGen/AArch64/vecreduce-add-legalization.ll
  test/CodeGen/AArch64/vecreduce-and-legalization.ll
  test/CodeGen/AArch64/vecreduce-bool.ll
  test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
  test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
  test/CodeGen/AArch64/vecreduce-umax-legalization.ll
  test/CodeGen/Generic/expand-experimental-reductions.ll
  test/CodeGen/X86/vector-reduce-add-widen.ll
  test/CodeGen/X86/vector-reduce-add.ll
  test/CodeGen/X86/vector-reduce-and-widen.ll
  test/CodeGen/X86/vector-reduce-and.ll
  test/CodeGen/X86/vector-reduce-fmax-nnan.ll
  test/CodeGen/X86/vector-reduce-fmax.ll
  test/CodeGen/X86/vector-reduce-fmin-nnan.ll
  test/CodeGen/X86/vector-reduce-fmin.ll
  test/CodeGen/X86/vector-reduce-mul-widen.ll
  test/CodeGen/X86/vector-reduce-mul.ll
  test/CodeGen/X86/vector-reduce-or-widen.ll
  test/CodeGen/X86/vector-reduce-or.ll
  test/CodeGen/X86/vector-reduce-smax-widen.ll
  test/CodeGen/X86/vector-reduce-smax.ll
  test/CodeGen/X86/vector-reduce-smin-widen.ll
  test/CodeGen/X86/vector-reduce-smin.ll
  test/CodeGen/X86/vector-reduce-umax-widen.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin-widen.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-reduce-xor-widen.ll
  test/CodeGen/X86/vector-reduce-xor.ll
  test/Transforms/LoopVectorize/AArch64/reduction-small-size.ll
  test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
  test/Transforms/SLPVectorizer/AArch64/gather-root.ll
  test/Transforms/SLPVectorizer/AArch64/horizontal.ll
  test/Transforms/SLPVectorizer/AArch64/transpose.ll
  utils/TableGen/IntrinsicEmitter.cpp