[llvm] r362700 - AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
Adhemerval Zanella via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 6 05:38:12 PDT 2019
Author: azanella
Date: Thu Jun 6 05:38:11 2019
New Revision: 362700
URL: http://llvm.org/viewvc/llvm-project?rev=362700&view=rev
Log:
AArch64] Handle ISD::LRINT and ISD::LLRINT for float16
This patch is a follow up for D62018 to add lrint/llrint
support for float16.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62863
Added:
llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll
llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=362700&r1=362699&r2=362700&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Jun 6 05:38:11 2019
@@ -3168,6 +3168,14 @@ let Predicates = [HasFRInt3264] in {
defm FRINT64X : FRIntNNT<0b11, "frint64x">;
} // HasFRInt3264
+let Predicates = [HasFullFP16] in {
+ def : Pat<(i32 (lrint f16:$Rn)),
+ (FCVTZSUWHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+ def : Pat<(i64 (lrint f16:$Rn)),
+ (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+ def : Pat<(i64 (llrint f16:$Rn)),
+ (FCVTZSUXHr (!cast<Instruction>(FRINTXHr) f16:$Rn))>;
+}
def : Pat<(i32 (lrint f32:$Rn)),
(FCVTZSUWSr (!cast<Instruction>(FRINTXSr) f32:$Rn))>;
def : Pat<(i32 (lrint f64:$Rn)),
Added: llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll?rev=362700&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/llrint-conv-fp16.ll Thu Jun 6 05:38:11 2019
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+ %conv = trunc i64 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+ %conv = trunc i64 %0 to i32
+ ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.llrint.i64.f16(half) nounwind readnone
Added: llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll?rev=362700&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16-win.ll Thu Jun 6 05:38:11 2019
@@ -0,0 +1,36 @@
+; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs w0, h0
+; CHECK-NEXT: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+ %conv = trunc i32 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs w0, h0
+; CHECK-NEXT: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+ ret i32 %0
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs w8, h0
+; CHECK-NEXT: sxtw x0, w8
+; CHECK-NEXT: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
+ %conv = sext i32 %0 to i64
+ ret i64 %conv
+}
+
+declare i32 @llvm.lrint.i32.f16(half) nounwind readnone
Added: llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll?rev=362700&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/lrint-conv-fp16.ll Thu Jun 6 05:38:11 2019
@@ -0,0 +1,35 @@
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s
+
+; CHECK-LABEL: testmhhs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i16 @testmhhs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+ %conv = trunc i64 %0 to i16
+ ret i16 %conv
+}
+
+; CHECK-LABEL: testmhws:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i32 @testmhws(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+ %conv = trunc i64 %0 to i32
+ ret i32 %conv
+}
+
+; CHECK-LABEL: testmhxs:
+; CHECK: frintx h0, h0
+; CHECK-NEXT: fcvtzs x0, h0
+; CHECK: ret
+define i64 @testmhxs(half %x) {
+entry:
+ %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
+ ret i64 %0
+}
+
+declare i64 @llvm.lrint.i64.f16(half) nounwind readnone
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