[PATCH] D62857: [RISCV] Prevent hoisting some adds after shifts

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:869
+
+        if (C1Seq.size() <= ShiftedC1Seq.size())
+          return false;
----------------
Isn't there an inaccuracy in this method of checking the materialization cost since `RISCVMatInt::generateInstSeq` always calculates the cost of materializing into a register? In this case we have instructions which might use immediates, but this will calculate the cost as being the same as a single-instruction materialization into a register followed by an instruction using a register.

IE:

```
addi rd, rs1, C
```

would appear to be the same cost as:

```
lui rs2, (C >> 12)
add rd, rs1, rs2
```



Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62857/new/

https://reviews.llvm.org/D62857