[llvm] r362690 - [MIPS GlobalISel] Select fabs
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 6 02:22:38 PDT 2019
Author: petar.avramovic
Date: Thu Jun 6 02:22:37 2019
New Revision: 362690
URL: http://llvm.org/viewvc/llvm-project?rev=362690&view=rev
Log:
[MIPS GlobalISel] Select fabs
Select G_FABS for MIPS32.
Differential Revision: https://reviews.llvm.org/D62903
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=362690&r1=362689&r2=362690&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Thu Jun 6 02:22:37 2019
@@ -357,6 +357,16 @@ bool MipsInstructionSelector::select(Mac
I.eraseFromParent();
return true;
}
+ case G_FABS: {
+ unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
+ unsigned FABSOpcode =
+ Size == 32 ? Mips::FABS_S
+ : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
+ MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
+ .add(I.getOperand(0))
+ .add(I.getOperand(1));
+ break;
+ }
case G_GLOBAL_VALUE: {
const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
if (MF.getTarget().isPositionIndependent()) {
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=362690&r1=362689&r2=362690&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Thu Jun 6 02:22:37 2019
@@ -94,7 +94,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
getActionDefinitionsBuilder(G_FCONSTANT)
.legalFor({s32, s64});
- getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
+ getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
.legalFor({s32, s64});
getActionDefinitionsBuilder(G_FCMP)
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=362690&r1=362689&r2=362690&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Thu Jun 6 02:22:37 2019
@@ -133,7 +133,8 @@ MipsRegisterBankInfo::getInstrMapping(co
case G_FADD:
case G_FSUB:
case G_FMUL:
- case G_FDIV: {
+ case G_FDIV:
+ case G_FABS: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
assert((Size == 32 || Size == 64) && "Unsupported floating point size");
OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir?rev=362690&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/fabs.mir Thu Jun 6 02:22:37 2019
@@ -0,0 +1,65 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fabs_f32() {entry: ret void}
+ define void @fabs_f64() {entry: ret void}
+
+...
+---
+name: fabs_f32
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fabs_f32
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP32: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
+ ; FP32: $f0 = COPY [[FABS_S]]
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fabs_f32
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
+ ; FP64: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
+ ; FP64: $f0 = COPY [[FABS_S]]
+ ; FP64: RetRA implicit $f0
+ %0:fprb(s32) = COPY $f12
+ %1:fprb(s32) = G_FABS %0
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
+---
+name: fabs_f64
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fabs_f64
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
+ ; FP32: [[FABS_D32_:%[0-9]+]]:afgr64 = FABS_D32 [[COPY]]
+ ; FP32: $d0 = COPY [[FABS_D32_]]
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fabs_f64
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
+ ; FP64: [[FABS_D64_:%[0-9]+]]:fgr64 = FABS_D64 [[COPY]]
+ ; FP64: $d0 = COPY [[FABS_D64_]]
+ ; FP64: RetRA implicit $d0
+ %0:fprb(s64) = COPY $d6
+ %1:fprb(s64) = G_FABS %0
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir?rev=362690&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/fabs.mir Thu Jun 6 02:22:37 2019
@@ -0,0 +1,61 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fabs_f32() {entry: ret void}
+ define void @fabs_f64() {entry: ret void}
+
+...
+---
+name: fabs_f32
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fabs_f32
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+ ; FP32: $f0 = COPY [[FABS]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fabs_f32
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
+ ; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
+ ; FP64: $f0 = COPY [[FABS]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = G_FABS %0
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
+---
+name: fabs_f64
+alignment: 2
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fabs_f64
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP32: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
+ ; FP32: $d0 = COPY [[FABS]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fabs_f64
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
+ ; FP64: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
+ ; FP64: $d0 = COPY [[FABS]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = G_FABS %0
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll?rev=362690&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll Thu Jun 6 02:22:37 2019
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+
+declare float @llvm.fabs.f32(float)
+define float @fabs_f32(float %a) {
+; MIPS32-LABEL: fabs_f32:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: abs.s $f0, $f12
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = call float @llvm.fabs.f32(float %a)
+ ret float %0
+}
+
+declare double @llvm.fabs.f64(double)
+define double @fabs_f64(double %a) {
+; MIPS32-LABEL: fabs_f64:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: abs.d $f0, $f12
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+entry:
+ %0 = call double @llvm.fabs.f64(double %a)
+ ret double %0
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir?rev=362690&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/fabs.mir Thu Jun 6 02:22:37 2019
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
+--- |
+
+ define void @fabs_f32() {entry: ret void}
+ define void @fabs_f64() {entry: ret void}
+
+...
+---
+name: fabs_f32
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $f12
+
+ ; FP32-LABEL: name: fabs_f32
+ ; FP32: liveins: $f12
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP32: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
+ ; FP32: $f0 = COPY [[FABS]](s32)
+ ; FP32: RetRA implicit $f0
+ ; FP64-LABEL: name: fabs_f32
+ ; FP64: liveins: $f12
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
+ ; FP64: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
+ ; FP64: $f0 = COPY [[FABS]](s32)
+ ; FP64: RetRA implicit $f0
+ %0:_(s32) = COPY $f12
+ %1:_(s32) = G_FABS %0
+ $f0 = COPY %1(s32)
+ RetRA implicit $f0
+
+...
+---
+name: fabs_f64
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+body: |
+ bb.1.entry:
+ liveins: $d6
+
+ ; FP32-LABEL: name: fabs_f64
+ ; FP32: liveins: $d6
+ ; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP32: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
+ ; FP32: $d0 = COPY [[FABS]](s64)
+ ; FP32: RetRA implicit $d0
+ ; FP64-LABEL: name: fabs_f64
+ ; FP64: liveins: $d6
+ ; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
+ ; FP64: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
+ ; FP64: $d0 = COPY [[FABS]](s64)
+ ; FP64: RetRA implicit $d0
+ %0:_(s64) = COPY $d6
+ %1:_(s64) = G_FABS %0
+ $d0 = COPY %1(s64)
+ RetRA implicit $d0
+
+...
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