[llvm] r362640 - AMDGPU: Fix using 2 different enums for same operand flags
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 5 13:32:25 PDT 2019
Author: arsenm
Date: Wed Jun 5 13:32:25 2019
New Revision: 362640
URL: http://llvm.org/viewvc/llvm-project?rev=362640&view=rev
Log:
AMDGPU: Fix using 2 different enums for same operand flags
These enums are really for the same namespace of flags set on
arbitrary MachineOperands, so merge them to avoid value collisions.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp?rev=362640&r1=362639&r2=362640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp Wed Jun 5 13:32:25 2019
@@ -112,10 +112,10 @@ const MCExpr *AMDGPUMCInstLower::getLong
const MCConstantExpr *One = MCConstantExpr::create(4, Ctx);
SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx);
- if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD)
+ if (MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_FORWARD)
return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx);
- assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD);
+ assert(MO.getTargetFlags() == SIInstrInfo::MO_LONG_BRANCH_BACKWARD);
return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx);
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=362640&r1=362639&r2=362640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Wed Jun 5 13:32:25 2019
@@ -1532,7 +1532,7 @@ unsigned SIInstrInfo::insertIndirectBran
BuildMI(MBB, I, DL, get(AMDGPU::S_ADD_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub0)
.addReg(PCReg, 0, AMDGPU::sub0)
- .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_FORWARD);
+ .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD);
BuildMI(MBB, I, DL, get(AMDGPU::S_ADDC_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub1)
.addReg(PCReg, 0, AMDGPU::sub1)
@@ -1542,7 +1542,7 @@ unsigned SIInstrInfo::insertIndirectBran
BuildMI(MBB, I, DL, get(AMDGPU::S_SUB_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub0)
.addReg(PCReg, 0, AMDGPU::sub0)
- .addMBB(&DestBB, AMDGPU::TF_LONG_BRANCH_BACKWARD);
+ .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD);
BuildMI(MBB, I, DL, get(AMDGPU::S_SUBB_U32))
.addReg(PCReg, RegState::Define, AMDGPU::sub1)
.addReg(PCReg, 0, AMDGPU::sub1)
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=362640&r1=362639&r2=362640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Wed Jun 5 13:32:25 2019
@@ -157,7 +157,10 @@ public:
MO_REL32 = 4,
MO_REL32_LO = 4,
// MO_REL32_HI -> symbol at rel32@hi -> R_AMDGPU_REL32_HI.
- MO_REL32_HI = 5
+ MO_REL32_HI = 5,
+
+ MO_LONG_BRANCH_FORWARD = 6,
+ MO_LONG_BRANCH_BACKWARD = 7
};
explicit SIInstrInfo(const GCNSubtarget &ST);
@@ -1030,12 +1033,6 @@ namespace AMDGPU {
const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
const uint64_t RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23);
- // For MachineOperands.
- enum TargetFlags {
- TF_LONG_BRANCH_FORWARD = 1 << 0,
- TF_LONG_BRANCH_BACKWARD = 1 << 1
- };
-
} // end namespace AMDGPU
namespace SI {
More information about the llvm-commits
mailing list