[PATCH] D59990: AMDGPU. Divergence driven ISel. Assign register class for cross block values according to the divergence.

[Samuel Pitoiset via Phabricator via llvm-commits]

hakzsam added a comment.

In D59990#1530603 <https://reviews.llvm.org/D59990#1530603>, @alex-t wrote:

> In D59990#1530511 <https://reviews.llvm.org/D59990#1530511>, @hakzsam wrote:
>
> > > I have updated the change ttps://reviews.llvm.org/D62614 this Sunday.
> > >  The new one takes completely different approach. I'd appreciate very much If you could try  it.
> >
> > D62614 <https://reviews.llvm.org/D62614> doesn't fix the issue.
>
>
> Okay. I'm about to start partial revert of the change. 
>  Could you please provide me test cases so that I can check if my further fixes help.


See below the good and bad outputs for one CTS failure:

GOOD: https://hastebin.com/muwuwivofu
BAD: https://hastebin.com/gofawejoku

Thanks again for looking into this.

Note that this change also breaks https://bugs.freedesktop.org/show_bug.cgi?id=110811


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59990/new/

https://reviews.llvm.org/D59990