[PATCH] D62592: [RISCV] Add assembler support for RVC HINT instructions

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added inline comments.


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Comment at: lib/Target/RISCV/RISCVInstrInfoC.td:577
+  let Inst{6-2} = imm{4-0};
+  let isAsmParserOnly = 1;
+}
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We could remove "let isAsmParserOnly = 1" and add "let Inst{11} = 0". So tablegen won't complain the encoding ambiguous and will invoke DecodeGPRX0RegisterClass in RISCVGenDisassemblerTables.inc.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62592/new/

https://reviews.llvm.org/D62592