[PATCH] D62818: [InstCombine] Change order of ICmp fold.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/Transforms/InstCombine/InstCombineCompares.cpp:1762-1778
+  // (X & (signbit >> Z)) == 0 -> (X << Z) >= 0
+  // (X & (signbit >> Z)) != 0 -> (X << Z) < 0
+  Value *Z;
+  bool IsYShift = true;
+  BinaryOperator *Shift = dyn_cast<BinaryOperator>(Y);
+  if (!Shift || !Shift->isShift()) {
+    Shift = dyn_cast<BinaryOperator>(X);
----------------
Eww, this looks too much like backend pattern matching :)
Here you want something more like
```

  // (V0 & (signbit l>> V1)) ==/!= 0 -> (V0 << V1) >=/< 0
  // (V0 & (signbit << V1)) ==/!= 0 -> (V0 l>> V1) >=/< 0
  Value *V0, *V1, *Shift, *Zero;
  ICmpInst::Predicate Pred;
  if (match(&Cmp,
            m_ICmp(Pred,
                   m_OneUse(m_c_And(
                       m_CombineAnd(
                           m_CombineAnd(m_Shift(m_SignMask(), m_Value(V1)),
                                        m_Value(Shift)),
                           m_CombineOr(m_Shl(m_Value(), m_Value()),
                                       m_LShr(m_Value(), m_Value()))),
                       m_Value(V0))),
                   m_CombineAnd(m_Zero(), m_Value(Zero)))) &&
      Cmp.isEquality(Pred)) {
    Value *NewShift = cast<Instruction>(Shift)->getOpcode() == Instruction::LShr
                          ? Builder.CreateShl(V0, V1)
                          : Builder.CreateLShr(V0, V1);
    ICmpInst::Predicate NewPred =
        Pred == CmpInst::ICMP_EQ ? CmpInst::ICMP_SGE : CmpInst::ICMP_SLT;
    return new ICmpInst(NewPred, NewShift, Zero);
  }
```


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62818/new/

https://reviews.llvm.org/D62818