[PATCH] D62871: [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold

Tue Jun 4 13:59:07 PDT 2019

lebedev.ri added a comment.

In D62871#1529899 <https://reviews.llvm.org/D62871#1529899>, @efriedma wrote:

> For the cases involving sign bits, are we actually expecting the IR to look like this when we reach SelectionDAG?  With some form of D62818 <https://reviews.llvm.org/D62818>, I would expect we end up with "icmp slt"...

Probably not, but that is what we end up with currently https://godbolt.org/z/IDhcTo
That does look like missing instcombine fold (+a fold that doesn't fire),
not sure if we want to also handle it here in backend.

>> AArch64 good except vectors (pattern with lshr improves, but shl symmetrically degrades)
> 
> AArch64 doesn't have separate shift left and shift right instructions; instead, it's based on the sign of the shift amount.  This can make the optimal pattern a little strange, yes.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62871/new/

https://reviews.llvm.org/D62871