[PATCH] D62669: [ARM] Set up infrastructure for MVE vector instructions.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:2183
+      unsigned NextOpIndex = Inst.getNumOperands();
+      const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
+      int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO);
----------------
I think this should be using MII.get(Inst.getOpcode()), if it can.


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Comment at: llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp:535
+    if (STI.getFeatureBits()[ARM::HasMVEIntegerOps] ||
+        STI.getFeatureBits()[ARM::HasMVEFloatOps])
+      return RegNo;
----------------
Does HasMVEFloatOps imply HasMVEIntegerOps?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62669/new/

https://reviews.llvm.org/D62669