[PATCH] D61935: Fixes PPC64 Tbegin disassembling

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

Doesn't look like a correct pattern update to me.



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Comment at: lib/Target/PowerPC/PPCInstrHTM.td:100
 // value of the MSR Transaction State (TS) bits that exist before the
 // instruction is executed.  For tbegin., the EQ bit in CR0 can be used
 // to determine whether the transaction was successfully started (0) or
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See comments here. How do you express the return value for success/failure now?


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Comment at: lib/Target/PowerPC/PPCInstrHTM.td:106
 def : Pat<(int_ppc_tbegin i32:$R),
-           (XORI
-             (EXTRACT_SUBREG (
-               TBEGIN (HTM_get_imm imm:$R)), sub_eq),
-            1)>;
+           (TBEGIN (HTM_get_imm imm:$R))>;
 
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Are you sure you can just remove the pattern to extract the EQ bits here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61935/new/

https://reviews.llvm.org/D61935