[llvm] r362494 - [NFC][Codegen] D62818 - also add tests with X being constant
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 4 04:44:50 PDT 2019
Author: lebedevri
Date: Tue Jun 4 04:44:50 2019
New Revision: 362494
URL: http://llvm.org/viewvc/llvm-project?rev=362494&view=rev
Log:
[NFC][Codegen] D62818 - also add tests with X being constant
For X86, these may be a 'BT' pattern, and in general, can cause
the transform to deadlock.
Modified:
llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
Modified: llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -302,6 +302,40 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #43605
+; CHECK-NEXT: movk w8, #43605, lsl #16
+; CHECK-NEXT: lsr w8, w8, w0
+; CHECK-NEXT: tst w8, #0x1
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: ret
+ %t0 = lshr i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const2_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w9, #43605
+; CHECK-NEXT: lsr w8, w8, w0
+; CHECK-NEXT: movk w9, #43605, lsl #16
+; CHECK-NEXT: tst w8, w9
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: ret
+ %t0 = lshr i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
Modified: llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -297,6 +297,40 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #43605
+; CHECK-NEXT: movk w8, #43605, lsl #16
+; CHECK-NEXT: lsl w8, w8, w0
+; CHECK-NEXT: tst w8, #0x1
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: ret
+ %t0 = shl i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; CHECK-LABEL: scalar_i32_x_is_const2_eq:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w9, #43605
+; CHECK-NEXT: lsl w8, w8, w0
+; CHECK-NEXT: movk w9, #43605, lsl #16
+; CHECK-NEXT: tst w8, w9
+; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: ret
+ %t0 = shl i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
Modified: llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -1120,6 +1120,111 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const_eq:
+; ARM6: @ %bb.0:
+; ARM6-NEXT: ldr r1, .LCPI18_0
+; ARM6-NEXT: mov r2, #1
+; ARM6-NEXT: bic r0, r2, r1, lsr r0
+; ARM6-NEXT: bx lr
+; ARM6-NEXT: .p2align 2
+; ARM6-NEXT: @ %bb.1:
+; ARM6-NEXT: .LCPI18_0:
+; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const_eq:
+; ARM78: @ %bb.0:
+; ARM78-NEXT: movw r1, #43605
+; ARM78-NEXT: mov r2, #1
+; ARM78-NEXT: movt r1, #43605
+; ARM78-NEXT: bic r0, r2, r1, lsr r0
+; ARM78-NEXT: bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const_eq:
+; THUMB6: @ %bb.0:
+; THUMB6-NEXT: ldr r1, .LCPI18_0
+; THUMB6-NEXT: lsrs r1, r0
+; THUMB6-NEXT: movs r2, #1
+; THUMB6-NEXT: ands r2, r1
+; THUMB6-NEXT: rsbs r0, r2, #0
+; THUMB6-NEXT: adcs r0, r2
+; THUMB6-NEXT: bx lr
+; THUMB6-NEXT: .p2align 2
+; THUMB6-NEXT: @ %bb.1:
+; THUMB6-NEXT: .LCPI18_0:
+; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const_eq:
+; THUMB78: @ %bb.0:
+; THUMB78-NEXT: movw r1, #43605
+; THUMB78-NEXT: movt r1, #43605
+; THUMB78-NEXT: lsr.w r0, r1, r0
+; THUMB78-NEXT: movs r1, #1
+; THUMB78-NEXT: bic.w r0, r1, r0
+; THUMB78-NEXT: bx lr
+ %t0 = lshr i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const2_eq:
+; ARM6: @ %bb.0:
+; ARM6-NEXT: ldr r2, .LCPI19_0
+; ARM6-NEXT: mov r1, #1
+; ARM6-NEXT: and r0, r2, r1, lsr r0
+; ARM6-NEXT: clz r0, r0
+; ARM6-NEXT: lsr r0, r0, #5
+; ARM6-NEXT: bx lr
+; ARM6-NEXT: .p2align 2
+; ARM6-NEXT: @ %bb.1:
+; ARM6-NEXT: .LCPI19_0:
+; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const2_eq:
+; ARM78: @ %bb.0:
+; ARM78-NEXT: movw r1, #43605
+; ARM78-NEXT: mov r2, #1
+; ARM78-NEXT: movt r1, #43605
+; ARM78-NEXT: and r0, r1, r2, lsr r0
+; ARM78-NEXT: clz r0, r0
+; ARM78-NEXT: lsr r0, r0, #5
+; ARM78-NEXT: bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB6: @ %bb.0:
+; THUMB6-NEXT: movs r1, #1
+; THUMB6-NEXT: lsrs r1, r0
+; THUMB6-NEXT: ldr r2, .LCPI19_0
+; THUMB6-NEXT: ands r2, r1
+; THUMB6-NEXT: rsbs r0, r2, #0
+; THUMB6-NEXT: adcs r0, r2
+; THUMB6-NEXT: bx lr
+; THUMB6-NEXT: .p2align 2
+; THUMB6-NEXT: @ %bb.1:
+; THUMB6-NEXT: .LCPI19_0:
+; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB78: @ %bb.0:
+; THUMB78-NEXT: movs r1, #1
+; THUMB78-NEXT: lsr.w r0, r1, r0
+; THUMB78-NEXT: movw r1, #43605
+; THUMB78-NEXT: movt r1, #43605
+; THUMB78-NEXT: ands r0, r1
+; THUMB78-NEXT: clz r0, r0
+; THUMB78-NEXT: lsrs r0, r0, #5
+; THUMB78-NEXT: bx lr
+ %t0 = lshr i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
@@ -1154,11 +1259,11 @@ define i1 @negative_scalar_i8_bitsinmidd
; THUMB6-NEXT: ands r2, r0
; THUMB6-NEXT: sxtb r0, r2
; THUMB6-NEXT: cmp r0, #0
-; THUMB6-NEXT: blt .LBB18_2
+; THUMB6-NEXT: blt .LBB20_2
; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: movs r0, #0
; THUMB6-NEXT: bx lr
-; THUMB6-NEXT: .LBB18_2:
+; THUMB6-NEXT: .LBB20_2:
; THUMB6-NEXT: movs r0, #1
; THUMB6-NEXT: bx lr
;
Modified: llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -1131,6 +1131,111 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const_eq:
+; ARM6: @ %bb.0:
+; ARM6-NEXT: ldr r1, .LCPI18_0
+; ARM6-NEXT: mov r2, #1
+; ARM6-NEXT: bic r0, r2, r1, lsl r0
+; ARM6-NEXT: bx lr
+; ARM6-NEXT: .p2align 2
+; ARM6-NEXT: @ %bb.1:
+; ARM6-NEXT: .LCPI18_0:
+; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const_eq:
+; ARM78: @ %bb.0:
+; ARM78-NEXT: movw r1, #43605
+; ARM78-NEXT: mov r2, #1
+; ARM78-NEXT: movt r1, #43605
+; ARM78-NEXT: bic r0, r2, r1, lsl r0
+; ARM78-NEXT: bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const_eq:
+; THUMB6: @ %bb.0:
+; THUMB6-NEXT: ldr r1, .LCPI18_0
+; THUMB6-NEXT: lsls r1, r0
+; THUMB6-NEXT: movs r2, #1
+; THUMB6-NEXT: ands r2, r1
+; THUMB6-NEXT: rsbs r0, r2, #0
+; THUMB6-NEXT: adcs r0, r2
+; THUMB6-NEXT: bx lr
+; THUMB6-NEXT: .p2align 2
+; THUMB6-NEXT: @ %bb.1:
+; THUMB6-NEXT: .LCPI18_0:
+; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const_eq:
+; THUMB78: @ %bb.0:
+; THUMB78-NEXT: movw r1, #43605
+; THUMB78-NEXT: movt r1, #43605
+; THUMB78-NEXT: lsl.w r0, r1, r0
+; THUMB78-NEXT: movs r1, #1
+; THUMB78-NEXT: bic.w r0, r1, r0
+; THUMB78-NEXT: bx lr
+ %t0 = shl i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; ARM6-LABEL: scalar_i32_x_is_const2_eq:
+; ARM6: @ %bb.0:
+; ARM6-NEXT: ldr r2, .LCPI19_0
+; ARM6-NEXT: mov r1, #1
+; ARM6-NEXT: and r0, r2, r1, lsl r0
+; ARM6-NEXT: clz r0, r0
+; ARM6-NEXT: lsr r0, r0, #5
+; ARM6-NEXT: bx lr
+; ARM6-NEXT: .p2align 2
+; ARM6-NEXT: @ %bb.1:
+; ARM6-NEXT: .LCPI19_0:
+; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; ARM78-LABEL: scalar_i32_x_is_const2_eq:
+; ARM78: @ %bb.0:
+; ARM78-NEXT: movw r1, #43605
+; ARM78-NEXT: mov r2, #1
+; ARM78-NEXT: movt r1, #43605
+; ARM78-NEXT: and r0, r1, r2, lsl r0
+; ARM78-NEXT: clz r0, r0
+; ARM78-NEXT: lsr r0, r0, #5
+; ARM78-NEXT: bx lr
+;
+; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB6: @ %bb.0:
+; THUMB6-NEXT: movs r1, #1
+; THUMB6-NEXT: lsls r1, r0
+; THUMB6-NEXT: ldr r2, .LCPI19_0
+; THUMB6-NEXT: ands r2, r1
+; THUMB6-NEXT: rsbs r0, r2, #0
+; THUMB6-NEXT: adcs r0, r2
+; THUMB6-NEXT: bx lr
+; THUMB6-NEXT: .p2align 2
+; THUMB6-NEXT: @ %bb.1:
+; THUMB6-NEXT: .LCPI19_0:
+; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
+;
+; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
+; THUMB78: @ %bb.0:
+; THUMB78-NEXT: movs r1, #1
+; THUMB78-NEXT: lsl.w r0, r1, r0
+; THUMB78-NEXT: movw r1, #43605
+; THUMB78-NEXT: movt r1, #43605
+; THUMB78-NEXT: ands r0, r1
+; THUMB78-NEXT: clz r0, r0
+; THUMB78-NEXT: lsrs r0, r0, #5
+; THUMB78-NEXT: bx lr
+ %t0 = shl i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
@@ -1165,11 +1270,11 @@ define i1 @negative_scalar_i8_bitsinmidd
; THUMB6-NEXT: ands r2, r0
; THUMB6-NEXT: sxtb r0, r2
; THUMB6-NEXT: cmp r0, #0
-; THUMB6-NEXT: blt .LBB18_2
+; THUMB6-NEXT: blt .LBB20_2
; THUMB6-NEXT: @ %bb.1:
; THUMB6-NEXT: movs r0, #0
; THUMB6-NEXT: bx lr
-; THUMB6-NEXT: .LBB18_2:
+; THUMB6-NEXT: .LBB20_2:
; THUMB6-NEXT: movs r0, #1
; THUMB6-NEXT: bx lr
;
Modified: llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -870,6 +870,91 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; X86-LABEL: scalar_i32_x_is_const_eq:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-NEXT: btl %eax, %ecx
+; X86-NEXT: setae %al
+; X86-NEXT: retl
+;
+; X64-LABEL: scalar_i32_x_is_const_eq:
+; X64: # %bb.0:
+; X64-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NEXT: btl %edi, %eax
+; X64-NEXT: setae %al
+; X64-NEXT: retq
+ %t0 = lshr i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; X86-NOBMI-LABEL: scalar_i32_x_is_const2_eq:
+; X86-NOBMI: # %bb.0:
+; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NOBMI-NEXT: movl $1, %eax
+; X86-NOBMI-NEXT: shrl %cl, %eax
+; X86-NOBMI-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-NOBMI-NEXT: sete %al
+; X86-NOBMI-NEXT: retl
+;
+; X86-BMI1-LABEL: scalar_i32_x_is_const2_eq:
+; X86-BMI1: # %bb.0:
+; X86-BMI1-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-BMI1-NEXT: movl $1, %eax
+; X86-BMI1-NEXT: shrl %cl, %eax
+; X86-BMI1-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI1-NEXT: sete %al
+; X86-BMI1-NEXT: retl
+;
+; X86-BMI12-LABEL: scalar_i32_x_is_const2_eq:
+; X86-BMI12: # %bb.0:
+; X86-BMI12-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-BMI12-NEXT: movl $1, %ecx
+; X86-BMI12-NEXT: shrxl %eax, %ecx, %eax
+; X86-BMI12-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI12-NEXT: sete %al
+; X86-BMI12-NEXT: retl
+;
+; X64-NOBMI-LABEL: scalar_i32_x_is_const2_eq:
+; X64-NOBMI: # %bb.0:
+; X64-NOBMI-NEXT: movl %edi, %ecx
+; X64-NOBMI-NEXT: movl $1, %eax
+; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
+; X64-NOBMI-NEXT: shrl %cl, %eax
+; X64-NOBMI-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NOBMI-NEXT: sete %al
+; X64-NOBMI-NEXT: retq
+;
+; X64-BMI1-LABEL: scalar_i32_x_is_const2_eq:
+; X64-BMI1: # %bb.0:
+; X64-BMI1-NEXT: movl %edi, %ecx
+; X64-BMI1-NEXT: movl $1, %eax
+; X64-BMI1-NEXT: # kill: def $cl killed $cl killed $ecx
+; X64-BMI1-NEXT: shrl %cl, %eax
+; X64-BMI1-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI1-NEXT: sete %al
+; X64-BMI1-NEXT: retq
+;
+; X64-BMI12-LABEL: scalar_i32_x_is_const2_eq:
+; X64-BMI12: # %bb.0:
+; X64-BMI12-NEXT: movl $1, %eax
+; X64-BMI12-NEXT: shrxl %edi, %eax, %eax
+; X64-BMI12-NEXT: testl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI12-NEXT: sete %al
+; X64-BMI12-NEXT: retq
+ %t0 = lshr i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
Modified: llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll?rev=362494&r1=362493&r2=362494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll Tue Jun 4 04:44:50 2019
@@ -818,6 +818,91 @@ define i1 @scalar_i8_signbit_ne(i8 %x, i
}
;------------------------------------------------------------------------------;
+; What if X is a constant too?
+;------------------------------------------------------------------------------;
+
+define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
+; X86-NOBMI-LABEL: scalar_i32_x_is_const_eq:
+; X86-NOBMI: # %bb.0:
+; X86-NOBMI-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-NOBMI-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-NOBMI-NEXT: shll %cl, %eax
+; X86-NOBMI-NEXT: testb $1, %al
+; X86-NOBMI-NEXT: sete %al
+; X86-NOBMI-NEXT: retl
+;
+; X86-BMI1-LABEL: scalar_i32_x_is_const_eq:
+; X86-BMI1: # %bb.0:
+; X86-BMI1-NEXT: movb {{[0-9]+}}(%esp), %cl
+; X86-BMI1-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X86-BMI1-NEXT: shll %cl, %eax
+; X86-BMI1-NEXT: testb $1, %al
+; X86-BMI1-NEXT: sete %al
+; X86-BMI1-NEXT: retl
+;
+; X86-BMI12-LABEL: scalar_i32_x_is_const_eq:
+; X86-BMI12: # %bb.0:
+; X86-BMI12-NEXT: movb {{[0-9]+}}(%esp), %al
+; X86-BMI12-NEXT: movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-BMI12-NEXT: shlxl %eax, %ecx, %eax
+; X86-BMI12-NEXT: testb $1, %al
+; X86-BMI12-NEXT: sete %al
+; X86-BMI12-NEXT: retl
+;
+; X64-NOBMI-LABEL: scalar_i32_x_is_const_eq:
+; X64-NOBMI: # %bb.0:
+; X64-NOBMI-NEXT: movl %edi, %ecx
+; X64-NOBMI-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NOBMI-NEXT: # kill: def $cl killed $cl killed $ecx
+; X64-NOBMI-NEXT: shll %cl, %eax
+; X64-NOBMI-NEXT: testb $1, %al
+; X64-NOBMI-NEXT: sete %al
+; X64-NOBMI-NEXT: retq
+;
+; X64-BMI1-LABEL: scalar_i32_x_is_const_eq:
+; X64-BMI1: # %bb.0:
+; X64-BMI1-NEXT: movl %edi, %ecx
+; X64-BMI1-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI1-NEXT: # kill: def $cl killed $cl killed $ecx
+; X64-BMI1-NEXT: shll %cl, %eax
+; X64-BMI1-NEXT: testb $1, %al
+; X64-BMI1-NEXT: sete %al
+; X64-BMI1-NEXT: retq
+;
+; X64-BMI12-LABEL: scalar_i32_x_is_const_eq:
+; X64-BMI12: # %bb.0:
+; X64-BMI12-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-BMI12-NEXT: shlxl %edi, %eax, %eax
+; X64-BMI12-NEXT: testb $1, %al
+; X64-BMI12-NEXT: sete %al
+; X64-BMI12-NEXT: retq
+ %t0 = shl i32 2857740885, %y
+ %t1 = and i32 %t0, 1
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
+; X86-LABEL: scalar_i32_x_is_const2_eq:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: movl $-1437226411, %ecx # imm = 0xAA55AA55
+; X86-NEXT: btl %eax, %ecx
+; X86-NEXT: setae %al
+; X86-NEXT: retl
+;
+; X64-LABEL: scalar_i32_x_is_const2_eq:
+; X64: # %bb.0:
+; X64-NEXT: movl $-1437226411, %eax # imm = 0xAA55AA55
+; X64-NEXT: btl %edi, %eax
+; X64-NEXT: setae %al
+; X64-NEXT: retq
+ %t0 = shl i32 1, %y
+ %t1 = and i32 %t0, 2857740885
+ %res = icmp eq i32 %t1, 0
+ ret i1 %res
+}
+
+;------------------------------------------------------------------------------;
; A few negative tests
;------------------------------------------------------------------------------;
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