[llvm] r362485 - [SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Tue Jun  4 03:17:56 2019
New Revision: 362485

URL: http://llvm.org/viewvc/llvm-project?rev=362485&view=rev
Log:
[SelectionDAG] ComputeNumSignBits - clang-format + improve *EXTLOAD comments. NFCI.

Pre-commit requested for D62777.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=362485&r1=362484&r2=362485&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jun  4 03:17:56 2019
@@ -3878,13 +3878,13 @@ unsigned SelectionDAG::ComputeNumSignBit
     if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
       unsigned ExtType = LD->getExtensionType();
       switch (ExtType) {
-        default: break;
-        case ISD::SEXTLOAD:    // '17' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp+1;
-        case ISD::ZEXTLOAD:    // '16' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp;
+      default: break;
+      case ISD::SEXTLOAD: // e.g. i16->i32 = '17' bits known.
+        Tmp = LD->getMemoryVT().getScalarSizeInBits();
+        return VTBits - Tmp + 1;
+      case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known.
+        Tmp = LD->getMemoryVT().getScalarSizeInBits();
+        return VTBits - Tmp;
       }
     }
   }