[PATCH] D62821: Workaround for PR41575: don't allow inlining of clear_cache on some platforms

[George Burgess IV via Phabricator via llvm-commits]

george.burgess.iv created this revision.
george.burgess.iv added a reviewer: t.p.northover.
Herald added subscribers: llvm-commits, kristof.beyls, krytarowski, javed.absar.
Herald added a project: LLVM.

As detailed in https://llvm.org/PR41575, this code shouldn't be relying on implicit saves/restores for the registers it uses  `__asm("rN")` on. There are a few ways forward with this, but until we land one of those, the ARM function call ABI appears to save us here. No pun intended. :)


https://reviews.llvm.org/D62821

Files:
  compiler-rt/lib/builtins/clear_cache.c


Index: compiler-rt/lib/builtins/clear_cache.c
===================================================================
--- compiler-rt/lib/builtins/clear_cache.c
+++ compiler-rt/lib/builtins/clear_cache.c
@@ -87,6 +87,11 @@
 // It is expected to invalidate the instruction cache for the
 // specified range.
 
+// PR41575: The implicit clobber of r7 here doesn't play nicely with inlining.
+// Until we determine a better way to fix that, this shouldn't be inlined.
+#if defined(__arm__) && defined(__linux__)
+NOINLINE
+#endif
 void __clear_cache(void *start, void *end) {
 #if __i386__ || __x86_64__ || defined(_M_IX86) || defined(_M_X64)
 // Intel processors have a unified instruction and data cache


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