[PATCH] D62818: [InstCombine] Allow ((X << Y) & SignMask) != 0 to be optimized as (X << Y) s< 0.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri requested changes to this revision.
lebedev.ri added a comment.
This revision now requires changes to proceed.

This looks like a missing backend-level transform, either a generic-one in DAGCombiner, or in `ARMISelLowering.cpp`.

This fix is not the right thing to do because even if you disable this fold,
you can still receive this 'bad' IR you are trying to avoid here,
and will still end up generating bad ASM.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62818/new/

https://reviews.llvm.org/D62818