[PATCH] D62777: [SelectionDAG] ComputeNumSignBits - support constant pool values from target

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri accepted this revision.
lebedev.ri added a comment.
This revision is now accepted and ready to land.

This looks good to me, but i won't claim to know all the details here, so would be good for someone else to confirm.



================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3882
+      default: break;
+      case ISD::SEXTLOAD: // '17' bits known
+        Tmp = LD->getMemoryVT().getScalarSizeInBits();
----------------
I realize this is not a new comment, but why '17'?
Does this only load 16-bit and extends to 32-bit?


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3882-3887
-        case ISD::SEXTLOAD:    // '17' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp+1;
-        case ISD::ZEXTLOAD:    // '16' bits known
-          Tmp = LD->getMemoryVT().getScalarSizeInBits();
-          return VTBits-Tmp;
----------------
lebedev.ri wrote:
> I realize this is not a new comment, but why '17'?
> Does this only load 16-bit and extends to 32-bit?
Precommit formatting-only changes?


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3893
+          Type *CstTy = Cst->getType();
+          if (CstTy->isVectorTy() &&
+              (NumElts * VTBits) == CstTy->getPrimitiveSizeInBits()) {
----------------
Do you want to defer to scalar case if it's splat?


================
Comment at: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:3911
+              }
+              return 1;
+            }
----------------
```
return 1; // Unhandled aggregate elt type. Conservatively assuming no bits match the sign bit.
```


Repository:
  rL LLVM

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  https://reviews.llvm.org/D62777/new/

https://reviews.llvm.org/D62777