[llvm] r362400 - [AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 3 06:51:24 PDT 2019
Author: dpreobra
Date: Mon Jun 3 06:51:24 2019
New Revision: 362400
URL: http://llvm.org/viewvc/llvm-project?rev=362400&view=rev
Log:
[AMDGPU][MC] Added support of SCC, VCCZ and EXECZ operands
See bug 39292: https://bugs.llvm.org/show_bug.cgi?id=39292
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D62660
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/trunk/test/MC/AMDGPU/literals.s
llvm/trunk/test/MC/Disassembler/AMDGPU/literal_gfx9.txt
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp Mon Jun 3 06:51:24 2019
@@ -678,6 +678,15 @@ AMDGPUAsmPrinter::SIFunctionResourceInfo
case AMDGPU::TMA_HI:
llvm_unreachable("trap handler registers should not be used");
+ case AMDGPU::SRC_VCCZ:
+ llvm_unreachable("src_vccz register should not be used");
+
+ case AMDGPU::SRC_EXECZ:
+ llvm_unreachable("src_execz register should not be used");
+
+ case AMDGPU::SRC_SCC:
+ llvm_unreachable("src_scc register should not be used");
+
default:
break;
}
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Jun 3 06:51:24 2019
@@ -1658,6 +1658,10 @@ static bool isInlineValue(unsigned Reg)
case AMDGPU::SRC_PRIVATE_LIMIT:
case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
return true;
+ case AMDGPU::SRC_VCCZ:
+ case AMDGPU::SRC_EXECZ:
+ case AMDGPU::SRC_SCC:
+ return true;
default:
return false;
}
@@ -1723,7 +1727,12 @@ static unsigned getSpecialRegForName(Str
.Case("lds_direct", AMDGPU::LDS_DIRECT)
.Case("src_lds_direct", AMDGPU::LDS_DIRECT)
.Case("m0", AMDGPU::M0)
- .Case("scc", AMDGPU::SCC)
+ .Case("vccz", AMDGPU::SRC_VCCZ)
+ .Case("src_vccz", AMDGPU::SRC_VCCZ)
+ .Case("execz", AMDGPU::SRC_EXECZ)
+ .Case("src_execz", AMDGPU::SRC_EXECZ)
+ .Case("scc", AMDGPU::SRC_SCC)
+ .Case("src_scc", AMDGPU::SRC_SCC)
.Case("tba", AMDGPU::TBA)
.Case("tma", AMDGPU::TMA)
.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
@@ -3878,6 +3887,12 @@ bool AMDGPUAsmParser::subtargetHasRegist
}
switch (RegNo) {
+ case AMDGPU::SRC_SHARED_BASE:
+ case AMDGPU::SRC_SHARED_LIMIT:
+ case AMDGPU::SRC_PRIVATE_BASE:
+ case AMDGPU::SRC_PRIVATE_LIMIT:
+ case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
+ return !isCI() && !isSI() && !isVI();
case AMDGPU::TBA:
case AMDGPU::TBA_LO:
case AMDGPU::TBA_HI:
@@ -3895,9 +3910,6 @@ bool AMDGPUAsmParser::subtargetHasRegist
break;
}
- if (isInlineValue(RegNo))
- return !isCI() && !isSI() && !isVI();
-
if (isCI())
return true;
Modified: llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp Mon Jun 3 06:51:24 2019
@@ -916,11 +916,9 @@ MCOperand AMDGPUDisassembler::decodeSpec
case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
- // ToDo: no support for vccz register
- case 251: break;
- // ToDo: no support for execz register
- case 252: break;
- case 253: return createRegOperand(SCC);
+ case 251: return createRegOperand(SRC_VCCZ);
+ case 252: return createRegOperand(SRC_EXECZ);
+ case 253: return createRegOperand(SRC_SCC);
case 254: return createRegOperand(LDS_DIRECT);
default: break;
}
@@ -942,6 +940,9 @@ MCOperand AMDGPUDisassembler::decodeSpec
case 237: return createRegOperand(SRC_PRIVATE_BASE);
case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
+ case 251: return createRegOperand(SRC_VCCZ);
+ case 252: return createRegOperand(SRC_EXECZ);
+ case 253: return createRegOperand(SRC_SCC);
default: break;
}
return errOperand(Val, "unknown operand encoding " + Twine(Val));
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Mon Jun 3 06:51:24 2019
@@ -281,8 +281,14 @@ void AMDGPUInstPrinter::printRegOperand(
case AMDGPU::VCC:
O << "vcc";
return;
- case AMDGPU::SCC:
- O << "scc";
+ case AMDGPU::SRC_VCCZ:
+ O << "src_vccz";
+ return;
+ case AMDGPU::SRC_EXECZ:
+ O << "src_execz";
+ return;
+ case AMDGPU::SRC_SCC:
+ O << "src_scc";
return;
case AMDGPU::EXEC:
O << "exec";
@@ -358,6 +364,8 @@ void AMDGPUInstPrinter::printRegOperand(
case AMDGPU::SCRATCH_WAVE_OFFSET_REG:
case AMDGPU::PRIVATE_RSRC_REG:
llvm_unreachable("pseudo-register should not ever be emitted");
+ case AMDGPU::SCC:
+ llvm_unreachable("pseudo scc should not ever be emitted");
default:
break;
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp Mon Jun 3 06:51:24 2019
@@ -2823,19 +2823,19 @@ bool SIInstrInfo::usesConstantBus(const
if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
- // FLAT_SCR is just an SGPR pair.
- if (!MO.isImplicit() && (MO.getReg() == AMDGPU::FLAT_SCR))
- return true;
-
- // EXEC register uses the constant bus.
- if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)
- return true;
+ // Null is free
+ if (MO.getReg() == AMDGPU::SGPR_NULL)
+ return false;
// SGPRs use the constant bus
- return (MO.getReg() == AMDGPU::VCC || MO.getReg() == AMDGPU::M0 ||
- (!MO.isImplicit() &&
- (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||
- AMDGPU::SGPR_64RegClass.contains(MO.getReg()))));
+ if (MO.isImplicit()) {
+ return MO.getReg() == AMDGPU::M0 ||
+ MO.getReg() == AMDGPU::VCC ||
+ MO.getReg() == AMDGPU::VCC_LO;
+ } else {
+ return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
+ AMDGPU::SReg_64RegClass.contains(MO.getReg());
+ }
}
static unsigned findImplicitSGPRRead(const MachineInstr &MI) {
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Mon Jun 3 06:51:24 2019
@@ -154,6 +154,11 @@ BitVector SIRegisterInfo::getReservedReg
// M0 has to be reserved so that llvm accepts it as a live-in into a block.
reserveRegisterTuples(Reserved, AMDGPU::M0);
+ // Reserve src_vccz, src_execz, src_scc.
+ reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ);
+ reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ);
+ reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC);
+
// Reserve the memory aperture registers.
reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE);
reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT);
Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Mon Jun 3 06:51:24 2019
@@ -69,7 +69,16 @@ def EXEC : RegisterWithSubRegs<"EXEC", [
let HWEncoding = 126;
}
-def SCC : SIReg<"scc", 253>;
+// 32-bit real registers, for MC only.
+// May be used with both 32-bit and 64-bit operands.
+def SRC_VCCZ : SIReg<"src_vccz", 251>;
+def SRC_EXECZ : SIReg<"src_execz", 252>;
+def SRC_SCC : SIReg<"src_scc", 253>;
+
+// 1-bit pseudo register, for codegen only.
+// Should never be emitted.
+def SCC : SIReg<"">;
+
def M0 : SIReg <"m0", 124>;
def SGPR_NULL : SIReg<"null", 125>;
@@ -448,7 +457,8 @@ def LDS_DIRECT_CLASS : RegisterClass<"AM
def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
(add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI, XNACK_MASK_LO, XNACK_MASK_HI,
SGPR_NULL, TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
- SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID)> {
+ SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT, SRC_POPS_EXITING_WAVE_ID,
+ SRC_VCCZ, SRC_EXECZ, SRC_SCC)> {
let AllocationPriority = 8;
}
Modified: llvm/trunk/test/MC/AMDGPU/literals.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/literals.s?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/literals.s (original)
+++ llvm/trunk/test/MC/AMDGPU/literals.s Mon Jun 3 06:51:24 2019
@@ -1,6 +1,6 @@
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI --check-prefix=CI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=GFX89
// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=GFX89 --check-prefix=GFX9
@@ -519,7 +519,125 @@ v_trunc_f64 v[0:1], 0x100000001
v_trunc_f64 v[0:1], 0x1fffffff000
//---------------------------------------------------------------------------//
-// named inline values like shared_base
+// named inline values: scc, vccz, execz
+//---------------------------------------------------------------------------//
+
+// SICI: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x00,0x00,0xfd]
+// GFX89: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd]
+buffer_atomic_add v0, off, s[0:3], scc offset:4095
+
+// SICI: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81]
+// GFX89: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81]
+s_add_i32 s0, vccz, s0
+
+// SICI: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81]
+// GFX89: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81]
+s_add_i32 s0, execz, s0
+
+// SICI: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81]
+// GFX89: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81]
+s_add_i32 s0, scc, s0
+
+// SICI: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x87]
+// GFX89: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x86]
+s_and_b64 s[0:1], s[0:1], src_vccz
+
+// SICI: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x87]
+// GFX89: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x86]
+s_and_b64 s[0:1], s[0:1], src_execz
+
+// SICI: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x87]
+// GFX89: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x86]
+s_and_b64 s[0:1], s[0:1], src_scc
+
+// NOSICI: error: instruction not supported on this GPU
+// GFX89: v_add_u16_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x4c]
+v_add_u16 v0, vccz, v0
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// GFX9: v_add_u16_sdwa v0, src_scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xfd,0x06,0x86,0x06]
+v_add_u16_sdwa v0, scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// GFX9: v_add_u16_sdwa v0, v0, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfa,0x01,0x4c,0x00,0x06,0x06,0x86]
+v_add_u16_sdwa v0, v0, scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+
+// NOSICIVI: error: instruction not supported on this GPU
+// GFX9: v_add_u32_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x68]
+v_add_u32 v0, execz, v0
+
+// NOSICIVI: error: instruction not supported on this GPU
+// GFX9: v_add_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xfd,0x00,0x02,0x00]
+v_add_u32_e64 v0, scc, v0
+
+// SICI: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0x44,0x7d]
+// GFX89: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0xc4,0x7d]
+v_cmp_eq_i64 vcc, scc, v[0:1]
+
+// NOSICI: error: instruction not supported on this GPU
+// GFX89: v_max_f16_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x5a]
+v_max_f16 v0, execz, v0
+
+// SICI: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x20]
+// GFX89: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x16]
+v_max_f32 v0, vccz, v0
+
+// SICI: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0xce,0xd2,0xfd,0x00,0x02,0x00]
+// GFX89: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xfd,0x00,0x02,0x00]
+v_max_f64 v[0:1], scc, v[0:1]
+
+// NOSICIVI: error: instruction not supported on this GPU
+// GFX9: v_pk_add_f16 v0, src_execz, v0 ; encoding: [0x00,0x00,0x8f,0xd3,0xfc,0x00,0x02,0x18]
+v_pk_add_f16 v0, execz, v0
+
+// NOSICI: error: not a valid operand
+// GFX89: v_ceil_f16_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x85,0xd1,0xfb,0x00,0x00,0x20]
+v_ceil_f16 v0, neg(vccz)
+
+// NOSICI: error: not a valid operand
+// GFX89: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0x85,0xd1,0xfd,0x00,0x00,0x00]
+v_ceil_f16 v0, abs(scc)
+
+// NOSI: error: not a valid operand
+// CI: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x30,0xd3,0xfc,0x00,0x00,0x00]
+// GFX89: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x58,0xd1,0xfc,0x00,0x00,0x00]
+v_ceil_f64 v[5:6], |execz|
+
+// NOSI: error: not a valid operand
+// CI: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x30,0xd3,0x6a,0x00,0x00,0x20]
+// GFX89: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x20]
+v_ceil_f64 v[5:6], -vcc
+
+// SICI: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x44,0xd3,0xfb,0x00,0x00,0x20]
+// GFX89: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x20]
+v_ceil_f32 v0, -vccz
+
+// SICI: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x44,0xd3,0xfc,0x00,0x00,0x00]
+// GFX89: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x5d,0xd1,0xfc,0x00,0x00,0x00]
+v_ceil_f32 v0, |execz|
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// GFX9: v_ceil_f16_sdwa v5, |src_vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfb,0x16,0xa6,0x00]
+v_ceil_f16_sdwa v5, |vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE
+
+// NOSICI: error: not a valid operand
+// NOVI: error: invalid operand for instruction
+// GFX9: v_ceil_f16_sdwa v5, -src_scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfd,0x16,0x96,0x00]
+v_ceil_f16_sdwa v5, -scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE
+
+// NOSICIVI: error: invalid operand for instruction
+// GFX9: v_ceil_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfb,0x16,0x86,0x00]
+v_ceil_f32_sdwa v5, vccz dst_sel:DWORD src0_sel:DWORD
+
+// NOSICIVI: error: invalid operand for instruction
+// GFX9: v_ceil_f32_sdwa v5, |src_execz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfc,0x16,0xa6,0x00]
+v_ceil_f32_sdwa v5, |execz| dst_sel:DWORD src0_sel:DWORD
+
+//---------------------------------------------------------------------------//
+// named inline values: shared_base, shared_limit, private_base, etc
//---------------------------------------------------------------------------//
// NOSICIVI: error: failed parsing operand.
@@ -659,6 +777,10 @@ v_ceil_f32_sdwa v5, |src_shared_base| ds
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_add_u32 v0, private_base, s0
+// NOSICIVI: error: instruction not supported on this GPU
+// NOGFX9: error: invalid operand (violates constant bus restrictions)
+v_add_u32 v0, scc, s0
+
// v_div_fmas implicitly reads VCC
// NOSICIVI: error: failed parsing operand.
// NOGFX9: error: invalid operand (violates constant bus restrictions)
@@ -674,6 +796,18 @@ v_div_fmas_f32 v0, v0, shared_limit, v1
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_div_fmas_f32 v0, v0, v1, private_limit
+// v_div_fmas implicitly reads VCC
+// NOGCN: error: invalid operand (violates constant bus restrictions)
+v_div_fmas_f32 v0, execz, v0, v1
+
+// v_div_fmas implicitly reads VCC
+// NOGCN: error: invalid operand (violates constant bus restrictions)
+v_div_fmas_f32 v0, v0, scc, v1
+
+// v_div_fmas implicitly reads VCC
+// NOGCN: error: invalid operand (violates constant bus restrictions)
+v_div_fmas_f32 v0, v0, v1, vccz
+
// v_addc_co_u32 implicitly reads VCC (VOP2)
// NOSICIVI: error: failed parsing operand.
// NOGFX9: error: invalid operand (violates constant bus restrictions)
@@ -683,6 +817,9 @@ v_addc_co_u32 v0, vcc, shared_base, v0,
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_madak_f32 v0, shared_base, v0, 0x11213141
+// NOGCN: error: invalid operand (violates constant bus restrictions)
+v_madak_f32 v0, scc, v0, 0x11213141
+
// NOSICIVI: error: failed parsing operand.
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32 s[0:1], private_base, private_limit
@@ -691,6 +828,13 @@ v_cmp_eq_f32 s[0:1], private_base, priva
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_cmp_eq_f32 s[0:1], private_base, s0
+// NOGCN: error: invalid operand (violates constant bus restrictions)
+v_cmp_eq_f32 s[0:1], execz, s0
+
// NOSICIVI: error: failed parsing operand.
// NOGFX9: error: invalid operand (violates constant bus restrictions)
v_pk_add_f16 v255, private_base, private_limit
+
+// NOSICIVI: error: instruction not supported on this GPU
+// NOGFX9: error: invalid operand (violates constant bus restrictions)
+v_pk_add_f16 v255, vccz, execz
Modified: llvm/trunk/test/MC/Disassembler/AMDGPU/literal_gfx9.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AMDGPU/literal_gfx9.txt?rev=362400&r1=362399&r2=362400&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AMDGPU/literal_gfx9.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AMDGPU/literal_gfx9.txt Mon Jun 3 06:51:24 2019
@@ -77,3 +77,84 @@
# GFX9: v_ceil_f32_sdwa v5, |src_shared_base| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0xa6,0x00]
0xf9,0x3a,0x0a,0x7e,0xeb,0x16,0xa6,0x00
+
+# GFX9: buffer_atomic_add v0, off, s[0:3], src_scc offset:4095 ; encoding: [0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd]
+0xff,0x0f,0x08,0xe1,0x00,0x00,0x00,0xfd
+
+# GFX9: s_add_i32 s0, src_vccz, s0 ; encoding: [0xfb,0x00,0x00,0x81]
+0xfb,0x00,0x00,0x81
+
+# GFX9: s_add_i32 s0, src_execz, s0 ; encoding: [0xfc,0x00,0x00,0x81]
+0xfc,0x00,0x00,0x81
+
+# GFX9: s_add_i32 s0, src_scc, s0 ; encoding: [0xfd,0x00,0x00,0x81]
+0xfd,0x00,0x00,0x81
+
+# GFX9: s_and_b64 s[0:1], s[0:1], src_vccz ; encoding: [0x00,0xfb,0x80,0x86]
+0x00,0xfb,0x80,0x86
+
+# GFX9: s_and_b64 s[0:1], s[0:1], src_execz ; encoding: [0x00,0xfc,0x80,0x86]
+0x00,0xfc,0x80,0x86
+
+# GFX9: s_and_b64 s[0:1], s[0:1], src_scc ; encoding: [0x00,0xfd,0x80,0x86]
+0x00,0xfd,0x80,0x86
+
+# GFX9: v_add_u16_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x4c]
+0xfb,0x00,0x00,0x4c
+
+# GFX9: v_add_u16_sdwa v0, src_scc, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x4c,0xfd,0x06,0x86,0x06]
+0xf9,0x00,0x00,0x4c,0xfd,0x06,0x86,0x06
+
+# GFX9: v_add_u16_sdwa v0, v0, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfa,0x01,0x4c,0x00,0x06,0x06,0x86]
+0xf9,0xfa,0x01,0x4c,0x00,0x06,0x06,0x86
+
+# GFX9: v_add_u32_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x68]
+0xfc,0x00,0x00,0x68
+
+# GFX9: v_add_u32_e64 v0, src_scc, v0 ; encoding: [0x00,0x00,0x34,0xd1,0xfd,0x00,0x02,0x00]
+0x00,0x00,0x34,0xd1,0xfd,0x00,0x02,0x00
+
+# GFX9: v_cmp_eq_i64_e32 vcc, src_scc, v[0:1] ; encoding: [0xfd,0x00,0xc4,0x7d]
+0xfd,0x00,0xc4,0x7d
+
+# GFX9: v_max_f16_e32 v0, src_execz, v0 ; encoding: [0xfc,0x00,0x00,0x5a]
+0xfc,0x00,0x00,0x5a
+
+# GFX9: v_max_f32_e32 v0, src_vccz, v0 ; encoding: [0xfb,0x00,0x00,0x16]
+0xfb,0x00,0x00,0x16
+
+# GFX9: v_max_f64 v[0:1], src_scc, v[0:1] ; encoding: [0x00,0x00,0x83,0xd2,0xfd,0x00,0x02,0x00]
+0x00,0x00,0x83,0xd2,0xfd,0x00,0x02,0x00
+
+# GFX9: v_pk_add_f16 v0, src_execz, v0 ; encoding: [0x00,0x00,0x8f,0xd3,0xfc,0x00,0x02,0x18]
+0x00,0x00,0x8f,0xd3,0xfc,0x00,0x02,0x18
+
+# GFX9: v_ceil_f16_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x85,0xd1,0xfb,0x00,0x00,0x20]
+0x00,0x00,0x85,0xd1,0xfb,0x00,0x00,0x20
+
+# GFX9: v_ceil_f16_e64 v0, |src_scc| ; encoding: [0x00,0x01,0x85,0xd1,0xfd,0x00,0x00,0x00]
+0x00,0x01,0x85,0xd1,0xfd,0x00,0x00,0x00
+
+# GFX9: v_ceil_f64_e64 v[5:6], |src_execz| ; encoding: [0x05,0x01,0x58,0xd1,0xfc,0x00,0x00,0x00]
+0x05,0x01,0x58,0xd1,0xfc,0x00,0x00,0x00
+
+# GFX9: v_ceil_f64_e64 v[5:6], -vcc ; encoding: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x20]
+0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x20
+
+# GFX9: v_ceil_f32_e64 v0, -src_vccz ; encoding: [0x00,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x20]
+0x00,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x20
+
+# GFX9: v_ceil_f32_e64 v0, |src_execz| ; encoding: [0x00,0x01,0x5d,0xd1,0xfc,0x00,0x00,0x00]
+0x00,0x01,0x5d,0xd1,0xfc,0x00,0x00,0x00
+
+# GFX9: v_ceil_f16_sdwa v5, |src_vccz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfb,0x16,0xa6,0x00]
+0xf9,0x8a,0x0a,0x7e,0xfb,0x16,0xa6,0x00
+
+# GFX9: v_ceil_f16_sdwa v5, -src_scc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x8a,0x0a,0x7e,0xfd,0x16,0x96,0x00]
+0xf9,0x8a,0x0a,0x7e,0xfd,0x16,0x96,0x00
+
+# GFX9: v_ceil_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfb,0x16,0x86,0x00]
+0xf9,0x3a,0x0a,0x7e,0xfb,0x16,0x86,0x00
+
+# GFX9: v_ceil_f32_sdwa v5, |src_execz| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x3a,0x0a,0x7e,0xfc,0x16,0xa6,0x00]
+0xf9,0x3a,0x0a,0x7e,0xfc,0x16,0xa6,0x00
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