[PATCH] D60705: [ARM] Turn some undefined encoding bits into 0s.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham marked 2 inline comments as done.
simon_tatham added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:895
      let Inst{19-16} = 0b1111; // Rn
+     let Inst{15}    = 0b0;
      let Inst{5-4} = opcod;
----------------
efriedma wrote:
> Can you use Unpredictable here?
No – this encoding is a subset of the ORR encoding, which is the one that v8.1-M has tightened up to make the 0 bit mandatory. If I turn this into a softfail, then the v8.1-M conditional select instructions added by D62667 will be mis-decoded as unpredictable variants of move or shift instructions.


================
Comment at: llvm/lib/Target/ARM/ARMInstrThumb2.td:1889
   let Inst{19-16} = 0b1111; // Rn
+  let Inst{15} = 0b0;
   let Inst{14-12} = 0b000;
----------------
efriedma wrote:
> Can you use Unpredictable here?
No – same reason as above.


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  https://reviews.llvm.org/D60705/new/

https://reviews.llvm.org/D60705