[llvm] r362365 - [AArch64] Check for simple type in FPToUInt

[Sam Parker via llvm-commits]

Author: sam_parker
Date: Mon Jun  3 01:49:17 2019
New Revision: 362365

URL: http://llvm.org/viewvc/llvm-project?rev=362365&view=rev
Log:
[AArch64] Check for simple type in FPToUInt

DAGCombiner was hitting a SimpleType assertion when trying to combine
a v3f32 before type legalization.

bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916

Differential Revision: https://reviews.llvm.org/D62734

Added:
    llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=362365&r1=362364&r2=362365&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Mon Jun  3 01:49:17 2019
@@ -9206,6 +9206,9 @@ static SDValue performFpToIntCombine(SDN
   if (!Subtarget->hasNEON())
     return SDValue();
 
+  if (!N->getValueType(0).isSimple())
+    return SDValue();
+
   SDValue Op = N->getOperand(0);
   if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
       Op.getOpcode() != ISD::FMUL)

Added: llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll?rev=362365&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll (added)
+++ llvm/trunk/test/CodeGen/AArch64/v3f-to-int.ll Mon Jun  3 01:49:17 2019
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: convert_v3f32
+; CHECK: strb
+; CHECK: strh
+define void @convert_v3f32() {
+entry:
+  br label %bb
+
+bb:
+  %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  %1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02>
+  %2 = fptoui <3 x float> %1 to <3 x i8>
+  %3 = bitcast i8* undef to <3 x i8>*
+  store <3 x i8> %2, <3 x i8>* %3, align 1
+  ret void
+}