[PATCH] D62707: [AMDGPU] Use InliningThresholdMultiplier for inline hint

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL362239: [AMDGPU] Use InliningThresholdMultiplier for inline hint (authored by rampitec, committed by ).
Herald added a project: LLVM.

Changed prior to commit:
  https://reviews.llvm.org/D62707?vs=202443&id=202450#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62707/new/

https://reviews.llvm.org/D62707

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPUInline.cpp
  llvm/trunk/test/Transforms/Inline/AMDGPU/inline-hint.ll


Index: llvm/trunk/test/Transforms/Inline/AMDGPU/inline-hint.ll
===================================================================
--- llvm/trunk/test/Transforms/Inline/AMDGPU/inline-hint.ll
+++ llvm/trunk/test/Transforms/Inline/AMDGPU/inline-hint.ll
@@ -0,0 +1,77 @@
+; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-inline --inline-threshold=1 --inlinehint-threshold=2 < %s | FileCheck %s
+
+define hidden <16 x i32> @div_hint(<16 x i32> %x, <16 x i32> %y) #0 {
+entry:
+  %div.1 = udiv <16 x i32> %x, %y
+  %div.2 = udiv <16 x i32> %div.1, %y
+  %div.3 = udiv <16 x i32> %div.2, %y
+  %div.4 = udiv <16 x i32> %div.3, %y
+  %div.5 = udiv <16 x i32> %div.4, %y
+  %div.6 = udiv <16 x i32> %div.5, %y
+  %div.7 = udiv <16 x i32> %div.6, %y
+  %div.8 = udiv <16 x i32> %div.7, %y
+  %div.9 = udiv <16 x i32> %div.8, %y
+  %div.10 = udiv <16 x i32> %div.9, %y
+  %div.11 = udiv <16 x i32> %div.10, %y
+  %div.12 = udiv <16 x i32> %div.11, %y
+  %div.13 = udiv <16 x i32> %div.12, %y
+  %div.14 = udiv <16 x i32> %div.13, %y
+  %div.15 = udiv <16 x i32> %div.14, %y
+  %div.16 = udiv <16 x i32> %div.15, %y
+  %div.17 = udiv <16 x i32> %div.16, %y
+  %div.18 = udiv <16 x i32> %div.17, %y
+  %div.19 = udiv <16 x i32> %div.18, %y
+  ret <16 x i32> %div.19
+}
+
+; CHECK-LABEL: define amdgpu_kernel void @caller_hint
+; CHECK-NOT: call
+; CHECK: udiv
+; CHECK: ret void
+define amdgpu_kernel void @caller_hint(<16 x i32> addrspace(1)* nocapture %x, <16 x i32> addrspace(1)* nocapture readonly %y) {
+entry:
+  %tmp = load <16 x i32>, <16 x i32> addrspace(1)* %x, align 4
+  %tmp1 = load <16 x i32>, <16 x i32> addrspace(1)* %y, align 4
+  %div.i = tail call <16 x i32> @div_hint(<16 x i32> %tmp, <16 x i32> %tmp1) #0
+  store <16 x i32> %div.i, <16 x i32> addrspace(1)* %x, align 4
+  ret void
+}
+
+define hidden <16 x i32> @div_nohint(<16 x i32> %x, <16 x i32> %y) {
+entry:
+  %div.1 = udiv <16 x i32> %x, %y
+  %div.2 = udiv <16 x i32> %div.1, %y
+  %div.3 = udiv <16 x i32> %div.2, %y
+  %div.4 = udiv <16 x i32> %div.3, %y
+  %div.5 = udiv <16 x i32> %div.4, %y
+  %div.6 = udiv <16 x i32> %div.5, %y
+  %div.7 = udiv <16 x i32> %div.6, %y
+  %div.8 = udiv <16 x i32> %div.7, %y
+  %div.9 = udiv <16 x i32> %div.8, %y
+  %div.10 = udiv <16 x i32> %div.9, %y
+  %div.11 = udiv <16 x i32> %div.10, %y
+  %div.12 = udiv <16 x i32> %div.11, %y
+  %div.13 = udiv <16 x i32> %div.12, %y
+  %div.14 = udiv <16 x i32> %div.13, %y
+  %div.15 = udiv <16 x i32> %div.14, %y
+  %div.16 = udiv <16 x i32> %div.15, %y
+  %div.17 = udiv <16 x i32> %div.16, %y
+  %div.18 = udiv <16 x i32> %div.17, %y
+  %div.19 = udiv <16 x i32> %div.18, %y
+  ret <16 x i32> %div.19
+}
+
+; CHECK-LABEL: define amdgpu_kernel void @caller_nohint
+; CHECK-NOT: udiv
+; CHECK: tail call <16 x i32> @div_nohint
+; CHECK: ret void
+define amdgpu_kernel void @caller_nohint(<16 x i32> addrspace(1)* nocapture %x, <16 x i32> addrspace(1)* nocapture readonly %y) {
+entry:
+  %tmp = load <16 x i32>, <16 x i32> addrspace(1)* %x
+  %tmp1 = load <16 x i32>, <16 x i32> addrspace(1)* %y
+  %div.i = tail call <16 x i32> @div_nohint(<16 x i32> %tmp, <16 x i32> %tmp1)
+  store <16 x i32> %div.i, <16 x i32> addrspace(1)* %x
+  ret void
+}
+
+attributes #0 = { inlinehint }
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUInline.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInline.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInline.cpp
@@ -111,7 +111,8 @@
     Callee->hasFnAttribute(Attribute::InlineHint);
   if (InlineHint && Params.HintThreshold && Params.HintThreshold > Thres
       && !Caller->hasFnAttribute(Attribute::MinSize))
-    Thres = Params.HintThreshold.getValue();
+    Thres = Params.HintThreshold.getValue() *
+            TTIWP->getTTI(*Callee).getInliningThresholdMultiplier();
 
   const DataLayout &DL = Caller->getParent()->getDataLayout();
   if (!Callee)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D62707.202450.patch
Type: text/x-patch
Size: 3905 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190531/d4e6e1bf/attachment.bin>