[PATCH] D62787: [X86] Add the vector integer min/max instructions to isAssociativeAndCommutative.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, andreadb.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

As far as I know these should be freely reassociatable just like
the floating point MAXC/MINC instructions.

The test changes demonstrate that something happened from this
patch, but I'm not sure we always made the right choice. I
think the fact that llc defaults to "generic" CPU is causing
us to not have a scheduler model so MachineCombiner doesn't
make the best decisions. But this isn't unique to these
instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D62787

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/test/CodeGen/X86/horizontal-reduce-smax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umax.ll
  llvm/test/CodeGen/X86/horizontal-reduce-umin.ll
  llvm/test/CodeGen/X86/vector-reduce-smax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-smax.ll
  llvm/test/CodeGen/X86/vector-reduce-smin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-smin.ll
  llvm/test/CodeGen/X86/vector-reduce-umax-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umax.ll
  llvm/test/CodeGen/X86/vector-reduce-umin-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-umin.ll

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