[llvm] r362275 - AMDGPU: Fix not adding ImplicitBufferPtr as a live-in

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Fri May 31 15:47:36 2019
New Revision: 362275

URL: http://llvm.org/viewvc/llvm-project?rev=362275&view=rev
Log:
AMDGPU: Fix not adding ImplicitBufferPtr as a live-in

Fixes missing test from r293000.

Added:
    llvm/trunk/test/CodeGen/AMDGPU/mesa3d.ll
Modified:
    llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp?rev=362275&r1=362274&r2=362275&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFrameLowering.cpp Fri May 31 15:47:36 2019
@@ -419,7 +419,7 @@ void SIFrameLowering::emitEntryFunctionS
       }
     }
     MF.getRegInfo().addLiveIn(GitPtrLo);
-    MF.front().addLiveIn(GitPtrLo);
+    MBB.addLiveIn(GitPtrLo);
     BuildMI(MBB, I, DL, SMovB32, RsrcLo)
       .addReg(GitPtrLo)
       .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
@@ -487,6 +487,9 @@ void SIFrameLowering::emitEntryFunctionS
           .addImm(0) // dlc
           .addMemOperand(MMO)
           .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
+
+        MF.getRegInfo().addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
+        MBB.addLiveIn(MFI->getImplicitBufferPtrUserSGPR());
       }
     } else {
       unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);

Added: llvm/trunk/test/CodeGen/AMDGPU/mesa3d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/mesa3d.ll?rev=362275&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/mesa3d.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/mesa3d.ll Fri May 31 15:47:36 2019
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}scratch_ps:
+; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0{{$}}
+; GCN-DAG: s_mov_b32 s6, -1{{$}}
+; GCN-DAG: s_mov_b32 s7, 0xe8f000
+; GCN-DAG: v_mov_b32_e32 [[V:v[0-9]+]], 2
+; GCN: buffer_store_dword [[V]], off, s[4:7], s2 offset:4
+define amdgpu_ps void @scratch_ps(i32 addrspace(1)* %out, i32 %in) {
+entry:
+  %alloca = alloca i32, addrspace(5)
+  store volatile i32 2, i32 addrspace(5)* %alloca
+  ret void
+}