[PATCH] D62740: [MIR-Canon] Don't do vreg skip for independent instructions if there are none.

[Puyan Lotfi via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL362247: [MIR-Canon] Don't do vreg skip for independent instructions if there are none. (authored by zer0, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D62740?vs=202451&id=202458#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62740/new/

https://reviews.llvm.org/D62740

Files:
  llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
  llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir


Index: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
@@ -743,7 +743,8 @@
   // of the MachineBasicBlock so that they are named in the order that we sorted
   // them alphabetically. Eventually we wont need SkipVRegs because we will use
   // named vregs instead.
-  NVC.SkipVRegs();
+  if (IdempotentInstCount)
+    NVC.SkipVRegs();
 
   auto MII = MBB->begin();
   for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {
Index: llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
@@ -1,4 +1,5 @@
 # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
 
 # Previously getReservedRegs was called before parsing
 # machineFunctionInfo, but the AMDGPU implementation depends on


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