[llvm] r362247 - [MIR-Canon] Don't do vreg skip for independent instructions if there are none.

[Puyan Lotfi via llvm-commits]

Author: zer0
Date: Fri May 31 10:34:25 2019
New Revision: 362247

URL: http://llvm.org/viewvc/llvm-project?rev=362247&view=rev
Log:
[MIR-Canon] Don't do vreg skip for independent instructions if there are none.

We don't want to create vregs if there is nothing to use them for. That causes
verifier errors.

Differential Revision: https://reviews.llvm.org/D62740



Modified:
    llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
    llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir

Modified: llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp?rev=362247&r1=362246&r2=362247&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRCanonicalizerPass.cpp Fri May 31 10:34:25 2019
@@ -743,7 +743,8 @@ static bool runOnBasicBlock(MachineBasic
   // of the MachineBasicBlock so that they are named in the order that we sorted
   // them alphabetically. Eventually we wont need SkipVRegs because we will use
   // named vregs instead.
-  NVC.SkipVRegs();
+  if (IdempotentInstCount)
+    NVC.SkipVRegs();
 
   auto MII = MBB->begin();
   for (unsigned i = 0; i < IdempotentInstCount && MII != MBB->end(); ++i) {

Modified: llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir?rev=362247&r1=362246&r2=362247&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir Fri May 31 10:34:25 2019
@@ -1,4 +1,5 @@
 # RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn  -run-pass mir-canonicalizer -verify-machineinstrs -o - %s
 
 # Previously getReservedRegs was called before parsing
 # machineFunctionInfo, but the AMDGPU implementation depends on