[PATCH] D62667: [ARM] Add the non-MVE instructions in Arm v8.1-M.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMRegisterInfo.td:264
+
+def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
+                                              LR, ZR)> {
----------------
simon_tatham wrote:
> samparker wrote:
> > I've just came here from the CSEL instructions, so forgive my limited scope, but why can't this register class access SP?
> It's used by the CSEL instructions themselves, and the vector/scalar forms of VCMP and VPT. VCMP can't access sp at all (the ArmARM says "see related encodings"), and all the others are listed as CONSTRAINED UNPREDICTABLE if you try.
cheers, I missed that bit and just saw that PC wasn't permitted.


Repository:
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  https://reviews.llvm.org/D62667/new/

https://reviews.llvm.org/D62667