[PATCH] D62651: [ARM] Add FP16 vector insert/extract patterns

Mikhail Maltsev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 31 03:55:40 PDT 2019


miyuki updated this revision to Diff 202412.
miyuki edited the summary of this revision.
miyuki added a comment.

Changed extraction patterns to avoid using GPRs as intermediate registers.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62651/new/

https://reviews.llvm.org/D62651

Files:
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/test/CodeGen/ARM/fp16-insert-extract.ll
  llvm/test/CodeGen/ARM/fp16-vldlane-vstlane.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D62651.202412.patch
Type: text/x-patch
Size: 8766 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190531/f6ffa76b/attachment.bin>


More information about the llvm-commits mailing list