[PATCH] D60705: [ARM] Turn some undefined encoding bits into 0s.
Simon Tatham via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 31 03:46:55 PDT 2019
simon_tatham updated this revision to Diff 202410.
simon_tatham added a comment.
If I set the Unpredictable field on the `ORR` instruction in particular, then it clashes with `CSEL`. But I think you're right that all the other affected instructions can be changed from `?` into `0` + Unpredictable.
Here's a revised version of the patch which does it that way, and also includes a test.
rG LLVM Github Monorepo
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