[PATCH] D62667: [ARM] Add the non-MVE instructions in Arm v8.1-M.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrVFP.td:2672
+                oops, !con(iops, (ins t2addrmode_imm7s4:$addr)),
+                IndexModePost, "$addr", "" > {
+    let DecoderMethod = "DecodeVSTRVLDR_SYSREG_off";
----------------
samparker wrote:
> Is this correct? What is IndexModePost?
So to answer my own question, this are bits defined in the Arm backend and are later used to populate the target-specific instruction flags. So I'm pretty certain that this should be IndexModeNone. Not sure of the real purpose of the flags though so I'm unsure how to test it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62667/new/

https://reviews.llvm.org/D62667