[llvm] r362127 - [AMDGPU] Added target-specific attribute amdgpu-max-memory-clause
Tim Renouf via llvm-commits
llvm-commits at lists.llvm.org
Thu May 30 11:46:34 PDT 2019
Author: tpr
Date: Thu May 30 11:46:34 2019
New Revision: 362127
URL: http://llvm.org/viewvc/llvm-project?rev=362127&view=rev
Log:
[AMDGPU] Added target-specific attribute amdgpu-max-memory-clause
With LLPC, previous investigation has suggested that si-scheduler
interacts badly with SiFormMemoryClauses on an XNACK target in some
games.
That needs further investigation in the future. In the meantime, this
commit adds a target-specific attribute to allow us to disable
SIFormMemoryClauses by setting it to 1 on a per-function basis for LLPC
to use.
Differential Revision: https://reviews.llvm.org/D62572
Change-Id: Ia0ca12ce79093cbbe86caded723ffb13384ede92
Added:
llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
Modified: llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp?rev=362127&r1=362126&r2=362127&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIFormMemoryClauses.cpp Thu May 30 11:46:34 2019
@@ -319,6 +319,8 @@ bool SIFormMemoryClauses::runOnMachineFu
MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();
+ unsigned FuncMaxClause = AMDGPU::getIntegerAttribute(
+ MF.getFunction(), "amdgpu-max-memory-clause", MaxClause);
for (MachineBasicBlock &MBB : MF) {
MachineBasicBlock::instr_iterator Next;
@@ -339,7 +341,7 @@ bool SIFormMemoryClauses::runOnMachineFu
continue;
unsigned Length = 1;
- for ( ; Next != E && Length < MaxClause; ++Next) {
+ for ( ; Next != E && Length < FuncMaxClause; ++Next) {
if (!isValidClauseInst(*Next, IsVMEM))
break;
Added: llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll?rev=362127&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/disable_form_clauses.ll Thu May 30 11:46:34 2019
@@ -0,0 +1,65 @@
+; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -amdgpu-enable-global-sgpr-addr -stop-after=si-form-memory-clauses < %s | FileCheck -check-prefix=GCN %s
+
+; GCN-LABEL: {{^}}name:{{[ ]*}}vector_clause
+; GCN: BUNDLE
+; GCN-NEXT: LOAD_DWORDX2
+; GCN-NEXT: LOAD_DWORDX2
+; GCN-NEXT: {{^ *[}]}}
+define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp2 = zext i32 %tmp to i64
+ %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
+ %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
+ %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
+ %tmp6 = add nuw nsw i64 %tmp2, 1
+ %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
+ %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
+ %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
+ %tmp10 = add nuw nsw i64 %tmp2, 2
+ %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
+ %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
+ %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
+ %tmp14 = add nuw nsw i64 %tmp2, 3
+ %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
+ %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
+ %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
+ store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
+ store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
+ store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
+ store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
+ ret void
+}
+
+; GCN-LABEL: {{^}}name:{{[ ]*}}no_vector_clause
+; GCN-NOT: BUNDLE
+define amdgpu_kernel void @no_vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) #0 {
+bb:
+ %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %tmp2 = zext i32 %tmp to i64
+ %tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
+ %tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
+ %tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
+ %tmp6 = add nuw nsw i64 %tmp2, 1
+ %tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
+ %tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
+ %tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
+ %tmp10 = add nuw nsw i64 %tmp2, 2
+ %tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
+ %tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
+ %tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
+ %tmp14 = add nuw nsw i64 %tmp2, 3
+ %tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
+ %tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
+ %tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
+ store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
+ store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
+ store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
+ store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
+ ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
+
+attributes #0 = { "amdgpu-max-memory-clause"="1" }
+
More information about the llvm-commits
mailing list