[llvm] r362114 - [NFC][Codegen] Potential add/sub constant folding: fixup non-splat tests

Roman Lebedev via llvm-commits llvm-commits at lists.llvm.org
Thu May 30 09:50:44 PDT 2019


Author: lebedevri
Date: Thu May 30 09:50:43 2019
New Revision: 362114

URL: http://llvm.org/viewvc/llvm-project?rev=362114&view=rev
Log:
[NFC][Codegen] Potential add/sub constant folding: fixup non-splat tests

Modified:
    llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll
    llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll

Modified: llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll?rev=362114&r1=362113&r2=362114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/addsub-constant-folding.ll Thu May 30 09:50:43 2019
@@ -94,10 +94,13 @@ define <4 x i32> @add_const_sub_const_no
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI5_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
-; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    adrp x8, .LCPI5_1
+; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI5_1]
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
   %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 
@@ -245,10 +248,13 @@ define <4 x i32> @sub_const_sub_const_no
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI14_0
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
-; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    adrp x8, .LCPI14_1
+; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI14_1]
+; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 
@@ -393,11 +399,11 @@ define <4 x i32> @const_sub_sub_const_no
 ; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
 ; CHECK-NEXT:    adrp x8, .LCPI23_1
 ; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI23_1]
-; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
-; CHECK-NEXT:    add v0.4s, v0.4s, v2.4s
+; CHECK-NEXT:    sub v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    sub v0.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    ret
   %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 

Modified: llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll?rev=362114&r1=362113&r2=362114&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll (original)
+++ llvm/trunk/test/CodeGen/X86/addsub-constant-folding.ll Thu May 30 09:50:43 2019
@@ -126,19 +126,17 @@ define <4 x i32> @add_const_sub_const_ex
 define <4 x i32> @add_const_sub_const_nonsplat(<4 x i32> %arg) {
 ; X86-LABEL: add_const_sub_const_nonsplat:
 ; X86:       # %bb.0:
-; X86-NEXT:    movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290>
-; X86-NEXT:    psubd %xmm0, %xmm1
-; X86-NEXT:    movdqa %xmm1, %xmm0
+; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
+; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: add_const_sub_const_nonsplat:
 ; X64:       # %bb.0:
-; X64-NEXT:    movdqa {{.*#+}} xmm1 = <4294967277,u,u,4294967290>
-; X64-NEXT:    psubd %xmm0, %xmm1
-; X64-NEXT:    movdqa %xmm1, %xmm0
+; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
+; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 
@@ -341,19 +339,17 @@ define <4 x i32> @sub_const_sub_const_ex
 define <4 x i32> @sub_const_sub_const_nonsplat(<4 x i32> %arg) {
 ; X86-LABEL: sub_const_sub_const_nonsplat:
 ; X86:       # %bb.0:
-; X86-NEXT:    movdqa {{.*#+}} xmm1 = <23,u,u,10>
-; X86-NEXT:    psubd %xmm0, %xmm1
-; X86-NEXT:    movdqa %xmm1, %xmm0
+; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
+; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: sub_const_sub_const_nonsplat:
 ; X64:       # %bb.0:
-; X64-NEXT:    movdqa {{.*#+}} xmm1 = <23,u,u,10>
-; X64-NEXT:    psubd %xmm0, %xmm1
-; X64-NEXT:    movdqa %xmm1, %xmm0
+; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
+; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
 ; X64-NEXT:    retq
   %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 
@@ -569,17 +565,21 @@ define <4 x i32> @const_sub_sub_const_ex
 define <4 x i32> @const_sub_sub_const_nonsplat(<4 x i32> %arg) {
 ; X86-LABEL: const_sub_sub_const_nonsplat:
 ; X86:       # %bb.0:
-; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm0
-; X86-NEXT:    paddd {{\.LCPI.*}}, %xmm0
+; X86-NEXT:    movdqa {{.*#+}} xmm1 = <21,u,8,8>
+; X86-NEXT:    psubd %xmm0, %xmm1
+; X86-NEXT:    psubd {{\.LCPI.*}}, %xmm1
+; X86-NEXT:    movdqa %xmm1, %xmm0
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: const_sub_sub_const_nonsplat:
 ; X64:       # %bb.0:
-; X64-NEXT:    psubd {{.*}}(%rip), %xmm0
-; X64-NEXT:    paddd {{.*}}(%rip), %xmm0
+; X64-NEXT:    movdqa {{.*#+}} xmm1 = <21,u,8,8>
+; X64-NEXT:    psubd %xmm0, %xmm1
+; X64-NEXT:    psubd {{.*}}(%rip), %xmm1
+; X64-NEXT:    movdqa %xmm1, %xmm0
 ; X64-NEXT:    retq
   %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg
-  %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
+  %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
   ret <4 x i32> %t1
 }
 




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