[llvm] r362097 - [ARM] Change the MC names for VMAXNM/VMINNM
Sjoerd Meijer via llvm-commits
llvm-commits at lists.llvm.org
Thu May 30 07:34:30 PDT 2019
Author: sjoerdmeijer
Date: Thu May 30 07:34:29 2019
New Revision: 362097
URL: http://llvm.org/viewvc/llvm-project?rev=362097&view=rev
Log:
[ARM] Change the MC names for VMAXNM/VMINNM
Now the NEON ones have a prefix "NEON_", and the VFP ones have a
prefix "VFP_". This is so that the regex in ARMScheduleA57.td can be
made to match both of _those_ classes of VMAXNM without also matching
the MVE ones that are going to be introduced soon. NFCI.
Patch by Simon Tatham.
Differential Revision: https://reviews.llvm.org/D60700
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
llvm/trunk/lib/Target/ARM/ARMScheduleA57.td
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=362097&r1=362096&r2=362097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu May 30 07:34:29 2019
@@ -5537,22 +5537,22 @@ def VMAXhq : N3VQInt<0, 0, 0b01, 0b11
// VMAXNM
let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
- def VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
- N3RegFrm, NoItinerary, "vmaxnm", "f32",
- v2f32, v2f32, fmaxnum, 1>,
- Requires<[HasV8, HasNEON]>;
- def VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
- N3RegFrm, NoItinerary, "vmaxnm", "f32",
- v4f32, v4f32, fmaxnum, 1>,
- Requires<[HasV8, HasNEON]>;
- def VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
- N3RegFrm, NoItinerary, "vmaxnm", "f16",
- v4f16, v4f16, fmaxnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
- def VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
- N3RegFrm, NoItinerary, "vmaxnm", "f16",
- v8f16, v8f16, fmaxnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
+ N3RegFrm, NoItinerary, "vmaxnm", "f32",
+ v2f32, v2f32, fmaxnum, 1>,
+ Requires<[HasV8, HasNEON]>;
+ def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
+ N3RegFrm, NoItinerary, "vmaxnm", "f32",
+ v4f32, v4f32, fmaxnum, 1>,
+ Requires<[HasV8, HasNEON]>;
+ def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1,
+ N3RegFrm, NoItinerary, "vmaxnm", "f16",
+ v4f16, v4f16, fmaxnum, 1>,
+ Requires<[HasV8, HasNEON, HasFullFP16]>;
+ def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1,
+ N3RegFrm, NoItinerary, "vmaxnm", "f16",
+ v8f16, v8f16, fmaxnum, 1>,
+ Requires<[HasV8, HasNEON, HasFullFP16]>;
}
// VMIN : Vector Minimum
@@ -5579,22 +5579,22 @@ def VMINhq : N3VQInt<0, 0, 0b11, 0b11
// VMINNM
let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
- def VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
- N3RegFrm, NoItinerary, "vminnm", "f32",
- v2f32, v2f32, fminnum, 1>,
- Requires<[HasV8, HasNEON]>;
- def VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
- N3RegFrm, NoItinerary, "vminnm", "f32",
- v4f32, v4f32, fminnum, 1>,
- Requires<[HasV8, HasNEON]>;
- def VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1,
- N3RegFrm, NoItinerary, "vminnm", "f16",
- v4f16, v4f16, fminnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
- def VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1,
- N3RegFrm, NoItinerary, "vminnm", "f16",
- v8f16, v8f16, fminnum, 1>,
- Requires<[HasV8, HasNEON, HasFullFP16]>;
+ def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
+ N3RegFrm, NoItinerary, "vminnm", "f32",
+ v2f32, v2f32, fminnum, 1>,
+ Requires<[HasV8, HasNEON]>;
+ def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
+ N3RegFrm, NoItinerary, "vminnm", "f32",
+ v4f32, v4f32, fminnum, 1>,
+ Requires<[HasV8, HasNEON]>;
+ def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1,
+ N3RegFrm, NoItinerary, "vminnm", "f16",
+ v4f16, v4f16, fminnum, 1>,
+ Requires<[HasV8, HasNEON, HasFullFP16]>;
+ def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1,
+ N3RegFrm, NoItinerary, "vminnm", "f16",
+ v8f16, v8f16, fminnum, 1>,
+ Requires<[HasV8, HasNEON, HasFullFP16]>;
}
// Vector Pairwise Operations.
Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=362097&r1=362096&r2=362097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Thu May 30 07:34:29 2019
@@ -533,8 +533,8 @@ multiclass vmaxmin_inst<string op, bit o
}
}
-defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
-defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
+defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
+defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
// Match reassociated forms only if not sign dependent rounding.
def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),
Modified: llvm/trunk/lib/Target/ARM/ARMScheduleA57.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMScheduleA57.td?rev=362097&r1=362096&r2=362097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMScheduleA57.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMScheduleA57.td Thu May 30 07:34:29 2019
@@ -1174,7 +1174,8 @@ def : InstRW<[A57Write_8cyc_1V], (instre
// ASIMD FP max/min
def : InstRW<[A57Write_5cyc_1V], (instregex
- "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "VMAXNM", "VMINNM")>;
+ "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "(NEON|VFP)_VMAXNM",
+ "(NEON|VFP)_VMINNM")>;
// ASIMD FP multiply
def A57WriteVMUL_VecFP : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
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