[PATCH] D62651: [ARM] Add FP16 vector insert/extract patterns
Mikhail Maltsev via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu May 30 04:42:21 PDT 2019
miyuki created this revision.
miyuki added a reviewer: eli.friedman.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.
This change adds two FP16 extraction and two insertion patterns
(one per possible vector length). 64-bit operations are handled by
existing i16 machinery with some conversion between GPRs and FP
registers (VMOVRH and VMOVHR insns). 128-bit vectors are handled
similarly, but the operation is only performed on one of the 64-bit
parts (using INSERT_SUBREG and EXTRACT_SUBREG with appropriate lane
Without these patterns the ARM backend would sometimes fail during
This patch also adds patterns which combine:
- an FP16 element extraction and a store into a single VST1 instruction
- an FP16 load and an insertion into a single VLD1 instruction
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