[llvm] r362053 - [X86] Add ENQCMD instructions
Pengfei Wang via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 20:59:17 PDT 2019
Author: pengfei
Date: Wed May 29 20:59:16 2019
New Revision: 362053
URL: http://llvm.org/viewvc/llvm-project?rev=362053&view=rev
Log:
[X86] Add ENQCMD instructions
For more details about these instructions, please refer to the latest
ISE document:
https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.
Patch by Tianqing Wang (tianqing)
Differential Revision: https://reviews.llvm.org/D62281
Added:
llvm/trunk/test/CodeGen/X86/enqcmd-intrinsics.ll
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsX86.td
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
llvm/trunk/test/MC/X86/x86-16.s
llvm/trunk/test/MC/X86/x86-32-coverage.s
llvm/trunk/test/MC/X86/x86-64.s
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Wed May 29 20:59:16 2019
@@ -4872,3 +4872,13 @@ let TargetPrefix = "x86" in {
Intrinsic<[llvm_v16f32_ty],
[llvm_v16f32_ty, llvm_v16i32_ty, llvm_v16i32_ty], [IntrNoMem]>;
}
+
+//===----------------------------------------------------------------------===//
+// ENQCMD - Enqueue Stores Instructions
+
+let TargetPrefix = "x86" in {
+ def int_x86_enqcmd : GCCBuiltin<"__builtin_ia32_enqcmd">,
+ Intrinsic<[llvm_i8_ty], [llvm_ptr_ty, llvm_ptr_ty], []>;
+ def int_x86_enqcmds : GCCBuiltin<"__builtin_ia32_enqcmds">,
+ Intrinsic<[llvm_i8_ty], [llvm_ptr_ty, llvm_ptr_ty], []>;
+}
Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Wed May 29 20:59:16 2019
@@ -1380,6 +1380,7 @@ bool sys::getHostCPUFeatures(StringMap<b
Features["cldemote"] = HasLeaf7 && ((ECX >> 25) & 1);
Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
+ Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
// There are two CPUID leafs which information associated with the pconfig
// instruction:
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Wed May 29 20:59:16 2019
@@ -263,6 +263,8 @@ def FeatureRDPID : SubtargetFeature<"rdp
"Support RDPID instructions">;
def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
"Wait and pause enhancements">;
+def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
+ "Has ENQCMD instructions">;
// On some processors, instructions that implicitly take two memory operands are
// slow. In practice, this means that CALL, PUSH, and POP with memory operands
// should be avoided in favor of a MOV + register CALL/PUSH/POP.
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed May 29 20:59:16 2019
@@ -2071,6 +2071,8 @@ bool X86DAGToDAGISel::selectAddr(SDNode
Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
+ Parent->getOpcode() != X86ISD::ENQCMD && // Fixme
+ Parent->getOpcode() != X86ISD::ENQCMDS && // Fixme
Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
unsigned AddrSpace =
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 29 20:59:16 2019
@@ -23290,6 +23290,27 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
Operation.getValue(1));
}
+ case Intrinsic::x86_enqcmd:
+ case Intrinsic::x86_enqcmds: {
+ SDLoc dl(Op);
+ SDValue Chain = Op.getOperand(0);
+ SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+ unsigned Opcode;
+ switch (IntNo) {
+ default: llvm_unreachable("Impossible intrinsic!");
+ case Intrinsic::x86_enqcmd:
+ Opcode = X86ISD::ENQCMD;
+ break;
+ case Intrinsic::x86_enqcmds:
+ Opcode = X86ISD::ENQCMDS;
+ break;
+ }
+ SDValue Operation = DAG.getNode(Opcode, dl, VTs, Chain, Op.getOperand(2),
+ Op.getOperand(3));
+ SDValue SetCC = getSETCC(X86::COND_E, Operation.getValue(0), dl, DAG);
+ return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), SetCC,
+ Operation.getValue(1));
+ }
}
return SDValue();
}
@@ -28270,6 +28291,8 @@ const char *X86TargetLowering::getTarget
case X86ISD::NT_BRIND: return "X86ISD::NT_BRIND";
case X86ISD::UMWAIT: return "X86ISD::UMWAIT";
case X86ISD::TPAUSE: return "X86ISD::TPAUSE";
+ case X86ISD::ENQCMD: return "X86ISD:ENQCMD";
+ case X86ISD::ENQCMDS: return "X86ISD:ENQCMDS";
}
return nullptr;
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed May 29 20:59:16 2019
@@ -589,6 +589,9 @@ namespace llvm {
// User level wait
UMWAIT, TPAUSE,
+ // Enqueue Stores Instructions
+ ENQCMD, ENQCMDS,
+
// Compare and swap.
LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
LCMPXCHG8_DAG,
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed May 29 20:59:16 2019
@@ -127,6 +127,9 @@ def SDT_X86TCRET : SDTypeProfile<0, 2, [
def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>;
+def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
+ SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>;
+
def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER,
[SDNPHasChain,SDNPSideEffect]>;
def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER,
@@ -307,6 +310,11 @@ def X86tpause : SDNode<"X86ISD::TPAUSE",
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
[SDNPHasChain, SDNPSideEffect]>;
+def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD,
+ [SDNPHasChain, SDNPSideEffect]>;
+def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD,
+ [SDNPHasChain, SDNPSideEffect]>;
+
//===----------------------------------------------------------------------===//
// X86 Operand Definitions.
//
@@ -900,6 +908,7 @@ def HasINVPCID : Predicate<"Subtarget-
def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
+def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
@@ -2756,6 +2765,37 @@ def MOVDIR64B64 : I<0xF8, MRMSrcMem, (ou
} // SchedRW
//===----------------------------------------------------------------------===//
+// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity
+//
+let SchedRW = [WriteStore], Defs = [EFLAGS] in {
+ def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>,
+ T8XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
+ def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>,
+ T8XD, AdSize32, Requires<[HasENQCMD]>;
+ def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
+ "enqcmd\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>,
+ T8XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
+
+ def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>,
+ T8XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>;
+ def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>,
+ T8XS, AdSize32, Requires<[HasENQCMD]>;
+ def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src),
+ "enqcmds\t{$src, $dst|$dst, $src}",
+ [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>,
+ T8XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>;
+}
+
+//===----------------------------------------------------------------------===//
// CLZERO Instruction
//
let SchedRW = [WriteSystem] in {
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Wed May 29 20:59:16 2019
@@ -356,6 +356,9 @@ protected:
/// Processor has AVX-512 bfloat16 floating-point extensions
bool HasBF16 = false;
+ /// Processor supports ENQCMD instructions
+ bool HasENQCMD = false;
+
/// Processor has AVX-512 Bit Algorithms instructions
bool HasBITALG = false;
@@ -688,6 +691,7 @@ public:
bool hasSGX() const { return HasSGX; }
bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
bool hasINVPCID() const { return HasINVPCID; }
+ bool hasENQCMD() const { return HasENQCMD; }
bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
bool useRetpolineIndirectBranches() const {
return UseRetpolineIndirectBranches;
Added: llvm/trunk/test/CodeGen/X86/enqcmd-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/enqcmd-intrinsics.ll?rev=362053&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/enqcmd-intrinsics.ll (added)
+++ llvm/trunk/test/CodeGen/X86/enqcmd-intrinsics.ll Wed May 29 20:59:16 2019
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+enqcmd | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+enqcmd | FileCheck %s --check-prefix=X32
+
+define i8 @test_enqcmd(i8* %dst, i8* %src) {
+entry:
+; X64-LABEL: test_enqcmd:
+; X64: # %bb.0: # %entry
+; X64-NEXT: enqcmd (%rsi), %rdi
+; X64-NEXT: sete %al
+; X64-NEXT: retq
+
+; X86-LABEL: test_enqcmd:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9+]}}(%esp), %eax
+; X86-NEXT: movl {{[0-9+]}}(%esp), %ecx
+; X86-NEXT: enqcmd (%eax), %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: retl
+
+; X32-LABEL: test_enqcmd:
+; X32: # %bb.0: # %entry
+; X32: enqcmd (%esi), %edi
+; X32-NEXT: sete %al
+; X32-NEXT: retq
+ %0 = call i8 @llvm.x86.enqcmd(i8* %dst, i8* %src)
+ ret i8 %0
+}
+
+define i8 @test_enqcmds(i8* %dst, i8* %src) {
+entry:
+; X64-LABEL: test_enqcmds:
+; X64: # %bb.0: # %entry
+; X64-NEXT: enqcmds (%rsi), %rdi
+; X64-NEXT: sete %al
+; X64-NEXT: retq
+
+; X86-LABEL: test_enqcmds:
+; X86: # %bb.0: # %entry
+; X86-NEXT: movl {{[0-9+]}}(%esp), %eax
+; X86-NEXT: movl {{[0-9+]}}(%esp), %ecx
+; X86-NEXT: enqcmds (%eax), %ecx
+; X86-NEXT: sete %al
+; X86-NEXT: retl
+
+; X32-LABEL: test_enqcmds:
+; X32: # %bb.0: # %entry
+; X32: enqcmds (%esi), %edi
+; X32-NEXT: sete %al
+; X32-NEXT: retq
+ %0 = call i8 @llvm.x86.enqcmds(i8* %dst, i8* %src)
+ ret i8 %0
+}
+
+declare i8 @llvm.x86.enqcmd(i8*, i8*)
+declare i8 @llvm.x86.enqcmds(i8*, i8*)
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-16.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-16.txt?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-16.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-16.txt Wed May 29 20:59:16 2019
@@ -806,3 +806,33 @@
#CHECK: movdir64b (%si), %ax
0x66 0x0f 0x38 0xf8 0x04
+
+# CHECK: enqcmd (%bx), %di
+0xf2,0x0f,0x38,0xf8,0x3f
+
+# CHECK: enqcmd 8128(%si), %ax
+0xf2,0x0f,0x38,0xf8,0x84,0xc0,0x1f
+
+# CHECK: enqcmd -8192(%di), %bx
+0xf2,0x0f,0x38,0xf8,0x9d,0x00,0xe0
+
+# CHECK: enqcmd 7408, %cx
+0xf2,0x0f,0x38,0xf8,0x0e,0xf0,0x1c
+
+# CHECK: enqcmds (%bx), %di
+0xf3,0x0f,0x38,0xf8,0x3f
+
+# CHECK: enqcmds 8128(%si), %ax
+0xf3,0x0f,0x38,0xf8,0x84,0xc0,0x1f
+
+# CHECK: enqcmds -8192(%di), %bx
+0xf3,0x0f,0x38,0xf8,0x9d,0x00,0xe0
+
+# CHECK: enqcmds 7408, %cx
+0xf3,0x0f,0x38,0xf8,0x0e,0xf0,0x1c
+
+# CHECK: enqcmd (%edi), %edi
+0x67,0xf2,0x0f,0x38,0xf8,0x3f
+
+# CHECK: enqcmds (%edi), %edi
+0x67,0xf3,0x0f,0x38,0xf8,0x3f
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Wed May 29 20:59:16 2019
@@ -901,3 +901,45 @@
# CHECK: addb $0, 305419896(,%eiz)
0x80 0x04 0x25 0x78 0x56 0x34 0x12 0x00
+
+# CHECK: enqcmd 268435456(%ebp,%eax,8), %esi
+0xf2,0x0f,0x38,0xf8,0xb4,0xc5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmd (%ecx), %edi
+0xf2,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmd 8128(%ecx), %eax
+0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmd -8192(%edx), %ebx
+0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmd 485498096, %eax
+0xf2,0x0f,0x38,0xf8,0x05,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: enqcmds 268435456(%ebp,%eax,8), %esi
+0xf3,0x0f,0x38,0xf8,0xb4,0xc5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmds (%ecx), %edi
+0xf3,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmds 8128(%ecx), %eax
+0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmds -8192(%edx), %ebx
+0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmds 485498096, %eax
+0xf3,0x0f,0x38,0xf8,0x05,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: enqcmd (%bx,%di), %di
+0x67,0xf2,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmd 8128(%bx,%di), %ax
+0x67,0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f
+
+# CHECK: enqcmds (%bx,%di), %di
+0x67,0xf3,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmds 8128(%bx,%di), %ax
+0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
Modified: llvm/trunk/test/MC/Disassembler/X86/x86-64.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-64.txt?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/x86-64.txt (original)
+++ llvm/trunk/test/MC/Disassembler/X86/x86-64.txt Wed May 29 20:59:16 2019
@@ -631,3 +631,63 @@
0x63 0x08
# CHECK: movslq (%rax), %cx
0x66 0x63 0x08
+
+# CHECK: enqcmd 485498096, %eax
+0x67,0xf2,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: enqcmd 268435456(%ebp,%r14d,8), %esi
+0x67,0xf2,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmd (%r9d), %edi
+0x67,0xf2,0x41,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmd 8128(%ecx), %eax
+0x67,0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmd -8192(%edx), %ebx
+0x67,0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmds 268435456(%ebp,%r14d,8), %esi
+0x67,0xf3,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmds (%r9d), %edi
+0x67,0xf3,0x41,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmds 8128(%ecx), %eax
+0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmds -8192(%edx), %ebx
+0x67,0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmds 485498096, %eax
+0x67,0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: enqcmd 268435456(%rbp,%r14,8), %rsi
+0xf2,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmd (%r9), %rdi
+0xf2,0x41,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmd 8128(%rcx), %rax
+0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmd -8192(%rdx), %rbx
+0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmd 485498096, %rax
+0xf2,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
+
+# CHECK: enqcmds 268435456(%rbp,%r14,8), %rsi
+0xf3,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10
+
+# CHECK: enqcmds (%r9), %rdi
+0xf3,0x41,0x0f,0x38,0xf8,0x39
+
+# CHECK: enqcmds 8128(%rcx), %rax
+0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00
+
+# CHECK: enqcmds -8192(%rdx), %rbx
+0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff
+
+# CHECK: enqcmds 485498096, %rax
+0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
Modified: llvm/trunk/test/MC/X86/x86-16.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-16.s?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-16.s (original)
+++ llvm/trunk/test/MC/X86/x86-16.s Wed May 29 20:59:16 2019
@@ -989,3 +989,43 @@ movdir64b (%esi), %eax
// CHECK: movdir64b (%si), %ax
// CHECK: encoding: [0x66,0x0f,0x38,0xf8,0x04]
movdir64b (%si), %ax
+
+// CHECK: enqcmd (%bx), %di
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x3f]
+enqcmd (%bx), %di
+
+// CHECK: enqcmd 8128(%si), %ax
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x84,0xc0,0x1f]
+enqcmd 8128(%si), %ax
+
+// CHECK: enqcmd -8192(%di), %bx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x9d,0x00,0xe0]
+enqcmd -8192(%di), %bx
+
+// CHECK: enqcmd 7408, %cx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x0e,0xf0,0x1c]
+enqcmd 7408, %cx
+
+// CHECK: enqcmds (%bx), %di
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x3f]
+enqcmds (%bx), %di
+
+// CHECK: enqcmds 8128(%si), %ax
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x84,0xc0,0x1f]
+enqcmds 8128(%si), %ax
+
+// CHECK: enqcmds -8192(%di), %bx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x9d,0x00,0xe0]
+enqcmds -8192(%di), %bx
+
+// CHECK: enqcmds 7408, %cx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x0e,0xf0,0x1c]
+enqcmds 7408, %cx
+
+// CHECK: enqcmd (%edi), %edi
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x3f]
+enqcmd (%edi), %edi
+
+// CHECK: enqcmds (%edi), %edi
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
+enqcmds (%edi), %edi
Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Wed May 29 20:59:16 2019
@@ -10816,3 +10816,59 @@ aam $10
// CHECK: aad # encoding: [0xd5,0x0a]
// INTEL: aad{{$}}
aad $10
+
+// CHECK: enqcmd 268435456(%ebp,%eax,8), %esi
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0xb4,0xc5,0x00,0x00,0x00,0x10]
+enqcmd 0x10000000(%ebp, %eax, 8), %esi
+
+// CHECK: enqcmd (%ecx), %edi
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x39]
+enqcmd (%ecx), %edi
+
+// CHECK: enqcmd 8128(%ecx), %eax
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmd 8128(%ecx), %eax
+
+// CHECK: enqcmd -8192(%edx), %ebx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmd -8192(%edx), %ebx
+
+// CHECK: enqcmd 485498096, %eax
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x05,0xf0,0x1c,0xf0,0x1c]
+enqcmd 485498096, %eax
+
+// CHECK: enqcmds 268435456(%ebp,%eax,8), %esi
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0xb4,0xc5,0x00,0x00,0x00,0x10]
+enqcmds 0x10000000(%ebp, %eax, 8), %esi
+
+// CHECK: enqcmds (%ecx), %edi
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x39]
+enqcmds (%ecx), %edi
+
+// CHECK: enqcmds 8128(%ecx), %eax
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmds 8128(%ecx), %eax
+
+// CHECK: enqcmds -8192(%edx), %ebx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmds -8192(%edx), %ebx
+
+// CHECK: enqcmds 485498096, %eax
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x05,0xf0,0x1c,0xf0,0x1c]
+enqcmds 485498096, %eax
+
+// CHECK: enqcmd (%bx,%di), %di
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x39]
+enqcmd (%bx,%di), %di
+
+// CHECK: enqcmd 8128(%bx,%di), %ax
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
+enqcmd 8128(%bx,%di), %ax
+
+// CHECK: enqcmds (%bx,%di), %di
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x39]
+enqcmds (%bx,%di), %di
+
+// CHECK: enqcmds 8128(%bx,%di), %ax
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
+enqcmds 8128(%bx,%di), %ax
Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=362053&r1=362052&r2=362053&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Wed May 29 20:59:16 2019
@@ -1797,3 +1797,83 @@ rep
// CHECK: lock
// This line has to be the last one in the file
lock
+
+// CHECK: enqcmd 268435456(%ebp,%r14d,8), %esi
+// CHECK: encoding: [0x67,0xf2,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
+enqcmd 0x10000000(%ebp, %r14d, 8), %esi
+
+// CHECK: enqcmd (%r9d), %edi
+// CHECK: encoding: [0x67,0xf2,0x41,0x0f,0x38,0xf8,0x39]
+enqcmd (%r9d), %edi
+
+// CHECK: enqcmd 8128(%ecx), %eax
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmd 8128(%ecx), %eax
+
+// CHECK: enqcmd -8192(%edx), %ebx
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmd -8192(%edx), %ebx
+
+// CHECK: enqcmd 485498096, %eax
+// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+enqcmd 485498096, %eax
+
+// CHECK: enqcmds 268435456(%ebp,%r14d,8), %esi
+// CHECK: encoding: [0x67,0xf3,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
+enqcmds 0x10000000(%ebp, %r14d, 8), %esi
+
+// CHECK: enqcmds (%r9d), %edi
+// CHECK: encoding: [0x67,0xf3,0x41,0x0f,0x38,0xf8,0x39]
+enqcmds (%r9d), %edi
+
+// CHECK: enqcmds 8128(%ecx), %eax
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmds 8128(%ecx), %eax
+
+// CHECK: enqcmds -8192(%edx), %ebx
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmds -8192(%edx), %ebx
+
+// CHECK: enqcmds 485498096, %eax
+// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+enqcmds 485498096, %eax
+
+// CHECK: enqcmd 268435456(%rbp,%r14,8), %rsi
+// CHECK: encoding: [0xf2,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
+enqcmd 0x10000000(%rbp, %r14, 8), %rsi
+
+// CHECK: enqcmd (%r9), %rdi
+// CHECK: encoding: [0xf2,0x41,0x0f,0x38,0xf8,0x39]
+enqcmd (%r9), %rdi
+
+// CHECK: enqcmd 8128(%rcx), %rax
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmd 8128(%rcx), %rax
+
+// CHECK: enqcmd -8192(%rdx), %rbx
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmd -8192(%rdx), %rbx
+
+// CHECK: enqcmd 485498096, %rax
+// CHECK: encoding: [0xf2,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+enqcmd 485498096, %rax
+
+// CHECK: enqcmds 268435456(%rbp,%r14,8), %rsi
+// CHECK: encoding: [0xf3,0x42,0x0f,0x38,0xf8,0xb4,0xf5,0x00,0x00,0x00,0x10]
+enqcmds 0x10000000(%rbp, %r14, 8), %rsi
+
+// CHECK: enqcmds (%r9), %rdi
+// CHECK: encoding: [0xf3,0x41,0x0f,0x38,0xf8,0x39]
+enqcmds (%r9), %rdi
+
+// CHECK: enqcmds 8128(%rcx), %rax
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f,0x00,0x00]
+enqcmds 8128(%rcx), %rax
+
+// CHECK: enqcmds -8192(%rdx), %rbx
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x9a,0x00,0xe0,0xff,0xff]
+enqcmds -8192(%rdx), %rbx
+
+// CHECK: enqcmds 485498096, %rax
+// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
+enqcmds 485498096, %rax
More information about the llvm-commits
mailing list