[llvm] r362019 - UpdateTestChecks: Lanai triple support
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed May 29 13:03:00 PDT 2019
Author: lebedevri
Date: Wed May 29 13:03:00 2019
New Revision: 362019
URL: http://llvm.org/viewvc/llvm-project?rev=362019&view=rev
Log:
UpdateTestChecks: Lanai triple support
Summary:
The assembly structure most resembles the SPARC pattern:
```
.globl f6 ! -- Begin function f6
.p2align 2
.type f6, at function
f6: ! @f6
.cfi_startproc
! %bb.0:
st %fp, [--%sp]
<...>
ld -8[%fp], %fp
.Lfunc_end0:
.size f6, .Lfunc_end0-f6
.cfi_endproc
! -- End function
```
Test being affected by upcoming patch, so regenerate it.
Reviewers: RKSimon, jpienaar
Reviewed By: RKSimon
Subscribers: jyknight, fedor.sergeev, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62545
Modified:
llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll
llvm/trunk/utils/UpdateTestChecks/asm.py
Modified: llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll?rev=362019&r1=362018&r2=362019&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll (original)
+++ llvm/trunk/test/CodeGen/Lanai/constant_multiply.ll Wed May 29 13:03:00 2019
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; Test custom lowering for 32-bit integer multiplication.
@@ -5,103 +6,191 @@
target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
target triple = "lanai"
-; CHECK-LABEL: f6:
-; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @f6(i32 inreg %a) #0 {
+; CHECK-LABEL: f6:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x1, %r3
+; CHECK-NEXT: sh %r6, 0x3, %r9
+; CHECK-NEXT: sub %r9, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, 6
ret i32 %1
}
-; CHECK-LABEL: f7:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r6, %rv
define i32 @f7(i32 inreg %a) #0 {
+; CHECK-LABEL: f7:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %r3
+; CHECK-NEXT: sub %r3, %r6, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, 7
ret i32 %1
}
-; CHECK-LABEL: f8:
-; CHECK: sh %r6, 0x3, %rv
define i32 @f8(i32 inreg %a) #0 {
+; CHECK-LABEL: f8:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = shl nsw i32 %a, 3
ret i32 %1
}
-; CHECK-LABEL: f9:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: add %r{{[0-9]+}}, %r6, %rv
define i32 @f9(i32 inreg %a) #0 {
+; CHECK-LABEL: f9:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %r3
+; CHECK-NEXT: add %r3, %r6, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, 9
ret i32 %1
}
-; CHECK-LABEL: f10:
-; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @f10(i32 inreg %a) #0 {
+; CHECK-LABEL: f10:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x1, %r3
+; CHECK-NEXT: sh %r6, 0x3, %r9
+; CHECK-NEXT: add %r9, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, 10
ret i32 %1
}
-; CHECK-LABEL: f1280:
-; CHECK: sh %r6, 0x8, %r{{[0-9]+}}
-; CHECK: sh %r6, 0xa, %r{{[0-9]+}}
-; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @f1280(i32 inreg %a) #0 {
+; CHECK-LABEL: f1280:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x8, %r3
+; CHECK-NEXT: sh %r6, 0xa, %r9
+; CHECK-NEXT: add %r9, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, 1280
ret i32 %1
}
-; CHECK-LABEL: fm6:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @fm6(i32 inreg %a) #0 {
+; CHECK-LABEL: fm6:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %r3
+; CHECK-NEXT: sh %r6, 0x1, %r9
+; CHECK-NEXT: sub %r9, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, -6
ret i32 %1
}
-; CHECK-LABEL: fm7:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r6, %r{{[0-9]+}}, %rv
define i32 @fm7(i32 inreg %a) #0 {
+; CHECK-LABEL: fm7:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %r3
+; CHECK-NEXT: sub %r6, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, -7
ret i32 %1
}
-; CHECK-LABEL: fm8:
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @fm8(i32 inreg %a) #0 {
+; CHECK-LABEL: fm8:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x3, %r3
+; CHECK-NEXT: sub %r0, %r3, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, -8
ret i32 %1
}
-; CHECK-LABEL: fm9:
-; CHECK: sub %r0, %r6, %r{{[0-9]+}}
-; CHECK: sh %r6, 0x3, %r9
-; CHECK: sub %r{{[0-9]+}}, %r9, %rv
define i32 @fm9(i32 inreg %a) #0 {
+; CHECK-LABEL: fm9:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sub %r0, %r6, %r3
+; CHECK-NEXT: sh %r6, 0x3, %r9
+; CHECK-NEXT: sub %r3, %r9, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, -9
ret i32 %1
}
-; CHECK-LABEL: fm10:
-; CHECK: sh %r6, 0x1, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}}
-; CHECK: sh %r6, 0x3, %r{{[0-9]+}}
-; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv
define i32 @fm10(i32 inreg %a) #0 {
+; CHECK-LABEL: fm10:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: sh %r6, 0x1, %r3
+; CHECK-NEXT: sub %r0, %r3, %r3
+; CHECK-NEXT: sh %r6, 0x3, %r9
+; CHECK-NEXT: sub %r3, %r9, %rv
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul nsw i32 %a, -10
ret i32 %1
}
-; CHECK-LABEL: h1:
-; CHECK: __mulsi3
define i32 @h1(i32 inreg %a) #0 {
+; CHECK-LABEL: h1:
+; CHECK: ! %bb.0:
+; CHECK-NEXT: st %fp, [--%sp]
+; CHECK-NEXT: add %sp, 0x8, %fp
+; CHECK-NEXT: sub %sp, 0x8, %sp
+; CHECK-NEXT: mov 0xaaaa0000, %r3
+; CHECK-NEXT: add %pc, 0x10, %rca
+; CHECK-NEXT: st %rca, [--%sp]
+; CHECK-NEXT: bt __mulsi3
+; CHECK-NEXT: or %r3, 0xaaab, %r7
+; CHECK-NEXT: ld -4[%fp], %pc ! return
+; CHECK-NEXT: add %fp, 0x0, %sp
+; CHECK-NEXT: ld -8[%fp], %fp
%1 = mul i32 %a, -1431655765
ret i32 %1
}
Modified: llvm/trunk/utils/UpdateTestChecks/asm.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/UpdateTestChecks/asm.py?rev=362019&r1=362018&r2=362019&view=diff
==============================================================================
--- llvm/trunk/utils/UpdateTestChecks/asm.py (original)
+++ llvm/trunk/utils/UpdateTestChecks/asm.py Wed May 29 13:03:00 2019
@@ -69,6 +69,13 @@ ASM_FUNCTION_RISCV_RE = re.compile(
r'.Lfunc_end[0-9]+:\n',
flags=(re.M | re.S))
+ASM_FUNCTION_LANAI_RE = re.compile(
+ r'^_?(?P<func>[^:]+):[ \t]*!+[ \t]*@(?P=func)\n'
+ r'(?:[ \t]+.cfi_startproc\n)?' # drop optional cfi noise
+ r'(?P<body>.*?)\s*'
+ r'.Lfunc_end[0-9]+:\n',
+ flags=(re.M | re.S))
+
ASM_FUNCTION_SPARC_RE = re.compile(
r'^_?(?P<func>[^:]+):[ \t]*!+[ \t]*@(?P=func)\n'
r'(?P<body>.*?)\s*'
@@ -186,6 +193,16 @@ def scrub_asm_riscv(asm, args):
asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
return asm
+def scrub_asm_lanai(asm, args):
+ # Scrub runs of whitespace out of the assembly, but leave the leading
+ # whitespace in place.
+ asm = common.SCRUB_WHITESPACE_RE.sub(r' ', asm)
+ # Expand the tabs used for indentation.
+ asm = string.expandtabs(asm, 2)
+ # Strip trailing whitespace.
+ asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
+ return asm
+
def scrub_asm_sparc(asm, args):
# Scrub runs of whitespace out of the assembly, but leave the leading
# whitespace in place.
@@ -266,6 +283,7 @@ def build_function_body_dictionary_for_t
'powerpc64le': (scrub_asm_powerpc, ASM_FUNCTION_PPC_RE),
'riscv32': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
'riscv64': (scrub_asm_riscv, ASM_FUNCTION_RISCV_RE),
+ 'lanai': (scrub_asm_lanai, ASM_FUNCTION_LANAI_RE),
'sparc': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
'sparcv9': (scrub_asm_sparc, ASM_FUNCTION_SPARC_RE),
's390x': (scrub_asm_systemz, ASM_FUNCTION_SYSTEMZ_RE),
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